Datasheet LTC1771 (Analog Devices) - 6

LTC1771
U OPERATIO (Refer to Functional Block Diagram) Main Control Loop
Burst Mode operation is provided by clamping the mini- mum I The LTC1771 uses a constant off-time, current mode TH voltage at 1V which represents about 25% of maximum load current. If the load falls below this level, i.e. step-down architecture. During normal operation, the the I P-channel MOSFET is turned on at the beginning of each TH voltage tries to fall below 1V, the burst comparator B switches state signaling the LTC1771 to enter sleep cycle and turned off when the current comparator C mode. During this time, EA is reduced to 10% of its normal triggers the 1-shot timer. The external MOSFET switch operating current and the external compensation capaci- stays off for the 3.5µs 1-shot duration and then turns back tor is disconnected and clamped to 1V so that the EA can on again to begin a new cycle. The peak inductor current drive its output with the lower available current. As the load at which C triggers the 1-shot is controlled by the voltage discharges the output capacitor, the internal I on Pin 3 (I TH voltage TH), the output of the error amplifier EA. An increases. When it exceeds 1V the burst comparator exits external resistive divider connected between VOUT and sleep mode, reconnects the external compensation com- ground allows EA to receive an output feedback voltage ponents to the error amplifier output, and returns EA to full VFB. When the load current increases, it causes a slight power along with the other necessary circuitry. This decrease in VFB relative to the 1.23V reference, which in scheme (patent pending) allows the EA to be reduced to turn causes the ITH voltage to increase until the average such a low operating current during sleep mode without inductor current matches the new load current. adding unacceptable delay to wake up the LTC1771 due to The main control loop is shut down by pulling Pin 1 the compensation capacitor on ITH required for stability in (RUN/SS) low. Releasing RUN/SS allows an internal 1µA normal operation. current source to charge soft-start capacitor CSS. When Burst Mode operation can be disabled by pulling the CSS reaches 1V, the main control loop is enabled with the MODE pin to ground. In this mode of operation, the burst ITH voltage clamped at approximately 40% of its maxi- comparator B is disabled and the I mum value. As C TH voltage allowed to go SS continues to charge, ITH is gradually all the way to 0V. The load can now be reduced to about 1% released allowing normal operation to resume. of maximum load before the loop skips cycles to maintain
Burst Mode Operation
regulation. This mode provides a low noise output spec- trum, useful for reducing both audio and RF interference, The LTC1771 provides outstanding low current efficiency at the expense of reduced efficiency at light loads. and ultralow no-load supply current by using Burst Mode operation when the MODE pin is pulled above 2V. During
Off-Time
Burst Mode operation, short burst cycles of normal switch- The off-time duration is 3.5µs when the feedback voltage ing are followed by a longer idle period with the switch off is close to the reference voltage; however, as the feedback and the load current is supplied by the output capacitor. voltage drops, the off-time lengthens and reaches a maxi- During this idle period, only the minimum required cir- mum value of about 70µs when V cuitry—1.23V reference and error amp—are left on, and FB is zero. This ensures that the inductor current has enough time to decay when the supply current is reduced to 9µA. At no load, the output the reverse voltage across the inductor is low such as capacitor is still discharged very slowly by leakage current during short circuit, thus protecting the MOSFET and in the Schottky diode and feedback resistor current result- inductor. ing in very low frequency burst cycles that add a few more microamps to the supply current. 6