Datasheet LT8710 (Analog Devices) - 10
| Hersteller | Analog Devices |
| Beschreibung | Synchronous SEPIC/Inverting/Boost Controller with Output Current Control |
| Seiten / Seite | 44 / 10 — pin FuncTions. RT (Pin 18):. SYNC (Pin 19):. MODE (Pin 17):. GND (Pin 20, … |
| Dateiformat / Größe | PDF / 657 Kb |
| Dokumentensprache | Englisch |
pin FuncTions. RT (Pin 18):. SYNC (Pin 19):. MODE (Pin 17):. GND (Pin 20, Exposed Pad Pin 21):. block DiagraM
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LT8710
pin FuncTions
used to limit the NFET current to avoid collapsing the
RT (Pin 18):
Timing Resistor Pin. Adjusts the LT8710’s input supply. Drive below 0.3V to disable the chip with switching frequency. Place a resistor from this pin to very low quiescent current. Drive above 1.7V (typical) to ground to set the frequency to a fixed free-running level. activate the chip and restart the soft-start sequence. The Do not float this pin. commanded NFET current will adjust when the EN/FBIN pin
SYNC (Pin 19):
To synchronize the switching frequency voltage drops between 1.55V and 1.662V. See the Block to an outside clock, simply drive this pin with a clock. The Diagram and Applications section for more information. high voltage level of the clock must exceed 1.5V, and the Do not float this pin. low level must be less than 0.4V. Drive this pin to less
MODE (Pin 17):
Forced CCM Mode Pin. Drive below 1.175V than 0.4V to revert to the internal free running clock. See (typical) to operate in forced CCM. Drive above 1.224V the Applications Information section for more information. (typical) to operate in DCM and/or pulse-skipping mode
GND (Pin 20, Exposed Pad Pin 21):
Ground. Must be at light loads. If SS < 1.8V (typical) or INTVEE is in UVLO, soldered directly to local ground plane. the part will operate in DCM at light load.
block DiagraM
C1 L1 V • L2 • IN VOUT CIN MP COUT MN R1 D1 C2 R R SENSE2 SENSE1 RFBX V CSP INTV IN CSN BG CC BIAS TG BIAS INTVCC DRIVER LEVEL CVEE BIAS DRIVER SHIFT LDO LDO LOGIC TG DRIVER BIAS – 6.18V INTVEE SR1 DISABLE UVLO Q – R S DCM_EN ISP ISN +A5 FLAG LDO DCM_EN INTV 6.3V CC + IMON CHRG 100µs – 666.5mV ANTI-GLITCH C A7 VCC UVLO 1.213V + – REFERENCE PG + IMON + 1.153V – 1.38V – RIN1 EN/FBIN EN/FBIN + DIE TEMP + LOGIC – 175°C – 68.5mV 51.5k R 1.213V IN2 1.3V 1.7V MODE + + EA1 14.5k SLOPE – 1.224V COMPENSATION – DCM_EN FBX + 1.8V ÷N ADJUSTABLE – OSCILLATOR + + 2.7V 50mV START-UP AND RESET – SS SOFT-START EA2 SYNC 14.5k LOGIC SS 260k BLOCK – + + DRIVER EN/FBIN 1.213V – ISN C DISABLE SS –EA4 EA3 – GND 1.607V A6 + +– ISP FBX FREQUENCY 11.9k DCM_EN FOLDBACK 51.8mV SYNC RT VC IMON 8710 BD RC RT CIMON CC CF
Figure 1. Block Diagram
8710f 10 For more information www.linear.com/LT8710
pin FuncTions
used to limit the NFET current to avoid collapsing the
RT (Pin 18):
Timing Resistor Pin. Adjusts the LT8710’s input supply. Drive below 0.3V to disable the chip with switching frequency. Place a resistor from this pin to very low quiescent current. Drive above 1.7V (typical) to ground to set the frequency to a fixed free-running level. activate the chip and restart the soft-start sequence. The Do not float this pin. commanded NFET current will adjust when the EN/FBIN pin
SYNC (Pin 19):
To synchronize the switching frequency voltage drops between 1.55V and 1.662V. See the Block to an outside clock, simply drive this pin with a clock. The Diagram and Applications section for more information. high voltage level of the clock must exceed 1.5V, and the Do not float this pin. low level must be less than 0.4V. Drive this pin to less
MODE (Pin 17):
Forced CCM Mode Pin. Drive below 1.175V than 0.4V to revert to the internal free running clock. See (typical) to operate in forced CCM. Drive above 1.224V the Applications Information section for more information. (typical) to operate in DCM and/or pulse-skipping mode
GND (Pin 20, Exposed Pad Pin 21):
Ground. Must be at light loads. If SS < 1.8V (typical) or INTVEE is in UVLO, soldered directly to local ground plane. the part will operate in DCM at light load.
block DiagraM
C1 L1 V • L2 • IN VOUT CIN MP COUT MN R1 D1 C2 R R SENSE2 SENSE1 RFBX V CSP INTV IN CSN BG CC BIAS TG BIAS INTVCC DRIVER LEVEL CVEE BIAS DRIVER SHIFT LDO LDO LOGIC TG DRIVER BIAS – 6.18V INTVEE SR1 DISABLE UVLO Q – R S DCM_EN ISP ISN +A5 FLAG LDO DCM_EN INTV 6.3V CC + IMON CHRG 100µs – 666.5mV ANTI-GLITCH C A7 VCC UVLO 1.213V + – REFERENCE PG + IMON + 1.153V – 1.38V – RIN1 EN/FBIN EN/FBIN + DIE TEMP + LOGIC – 175°C – 68.5mV 51.5k R 1.213V IN2 1.3V 1.7V MODE + + EA1 14.5k SLOPE – 1.224V COMPENSATION – DCM_EN FBX + 1.8V ÷N ADJUSTABLE – OSCILLATOR + + 2.7V 50mV START-UP AND RESET – SS SOFT-START EA2 SYNC 14.5k LOGIC SS 260k BLOCK – + + DRIVER EN/FBIN 1.213V – ISN C DISABLE SS –EA4 EA3 – GND 1.607V A6 + +– ISP FBX FREQUENCY 11.9k DCM_EN FOLDBACK 51.8mV SYNC RT VC IMON 8710 BD RC RT CIMON CC CF
Figure 1. Block Diagram
8710f 10 For more information www.linear.com/LT8710