Datasheet LT8570, LT8570-1 (Analog Devices) - 10

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APPLICATIONS INFORMATION Setting Output Voltage
For the SEPIC or dual inductor inverting topology (see Figure 1 and Figure 2): The output voltage is set by connecting a resistor (RFBX) from V V OUT to the FBX pin. RFBX is determined from the DC ≅ D + |VOUT| following equation: VIN + |VOUT| + VD − VCESAT |V R OUT − VFBX| The LT8570/LT8570-1 can be used in configurations FBX = 83.3µA where the duty cycle is higher than DCMAX, but it must be operated in the discontinuous conduction mode so that where VFBX is 1.204V (typical) for noninverting topologies the effective duty cycle is reduced. (i.e., boost and SEPIC regulators) and 3mV (typical) for inverting topologies (see the Electrical Characteristics).
Inductor Selection Power Switch Duty Cycle
General Guidelines: The high frequency operation of the LT8570/LT8570-1 allows for the use of small surface mount In order to maintain loop stability and deliver adequate inductors. For high efficiency, choose inductors with high current to the load, the power NPN (Q1 in the Block Dia- frequency core material, such as ferrite, to reduce core gram) cannot remain “on” for 100% of each clock cycle. losses. To improve efficiency, choose inductors with more The maximum allowable duty cycle is given by: volume for a given inductance. The inductor should have (TP − MinOff Time) low DCR (copper wire resistance) to reduce I2R losses, and DCMAX = • 100% T must be able to handle the peak inductor current without P saturating. Note that in some applications, the current where TP is the clock period and Min Off Time (found in handling requirements of the inductor can be lower, such the Electrical Characteristics) is typically 100ns. as in the SEPIC topology, where each inductor only carries The application should be designed so that the operating a fraction of the total switch current. Multilayer or chip duty cycle does not exceed DC inductors usually do not have enough core area to sup- MAX. port peak inductor currents in the 0.25A to 1A range. To The minimum allowable duty cycle is given by: minimize radiated noise, use a toroidal or shielded induc- Min On Time tor. Note that the inductance of shielded types will drop DCMIN = •100% more as current increases, and will saturate more easily. TP See Table 1 for a list of inductor manufacturers. Thorough where TP is the clock period and Min On-Time is as shown lab evaluation is recommended to verify that the following in the Typical Performance Characteristics. guidelines properly suit the final application. The application should be designed so that the operating
Table 1. Inductor Manufacturers
duty cycle is at least DCMIN. Coilcraft LPS5030, MSS7341, LPS4018, www.coilcraft.com LPD6235 and LPD5030 Series Duty cycle equations for several common topologies are Coiltronics DR, DRQ, SD and SDQ Series www.coiltronics.com given below, where VD is the diode forward voltage drop Sumida CDRH8D58/LD, CDRH64B, and www.sumida.com and VCESAT is typically 250mV at 0.4A for the LT8570 and CDRH70D430MN Series 250mV at 0.2A for the LT8570-1. Würth WE-PD, WE-DD, WE-TPC, www.we-online.com WE-LHMI and WE-LQS Series For the boost topology: VOUT − VIN + VD Minimum Inductance: Although there can be a trade-off DC ≅ V with efficiency, it is often desirable to minimize board OUT + VD − VCESAT space by choosing smaller inductors. When choosing an inductor, there are two conditions that limit the mini- mum inductance: (1) providing adequate load current, 85701fa 10 For more information www.linear.com/LT8570 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Revision History Typical Application Related Parts