Datasheet LT3959 (Analog Devices) - 7

LT3959
pin FuncTions DRIVE:
DRIVE LDO Supply Pin. This pin can be connected
NC:
No Internal Connection. Leave these pins open or to either VIN or a quasi-regulated voltage supply such as a connect them to the adjacent pins. DC converter output. This pin must be bypassed to GND
PGOOD:
Output Ready Status Pin. An open-collector pull with a minimum of 1µF capacitor placed close to the pin. down on PGOOD asserts when INTV Tie this pin to V CC is greater than IN if not used. 2.7V and the FBX voltage is within 5% (80mV if VFBX =
EN/UVLO:
Shutdown and Undervoltage Detect Pin. An 1.6V or 40mV if VFBX = –0.8V) of the regulation voltage. accurate 1.22V (nominal) falling threshold with externally
RT:
Switching Frequency Adjustment Pin. Set the frequency programmable hysteresis detects when power is okay to using a resistor to SGND. Do not leave the RT pin open. enable switching. Rising hysteresis is generated by the external resistor divider and an accurate internal 2.2μA
SGND:
Signal Ground. Must be soldered directly to the pull-down current. An undervoltage condition resets soft- signal ground plane. Connect to ground terminal of: ex- start. Tie to 0.4V, or less, to disable the device and reduce ternal resistor dividers for FBX and EN/UVLO; capacitors VIN quiescent current below 1μA. for INTVCC, SS, and VC; and resistor RT.
FBX:
Voltage Regulation Feedback Pin for Positive or
SS:
Soft-Start Pin. This pin modulates compensation pin Negative Outputs. Connect this pin to a resistor divider voltage (VC) clamp. The soft-start interval is set with an between the output and SGND. FBX is the input of two error external capacitor. The pin has a 10µA (typical) pull-up amplifiers—one configured to regulate a positive output; current source to an internal 2.5V rail. The soft-start pin the other, a negative output. Depending upon topology is reset to SGND by an EN/UVLO undervoltage condition, selected, switching causes the output to ramp positive or an INTVCC undervoltage condition or an internal thermal negative. The appropriate amplifier takes control while the lockout. other becomes inactive. Additionally FBX is input for two
SW:
Drain of Internal Power N-Channel MOSFET. window comparators that indicate through the PGOOD pin when the output is within 5% of the regulation volt-
SYNC:
Frequency Synchronization Pin. Used to synchronize ages. FBX also modulates the switching frequency during the internal oscillator to an outside clock. If this feature is start-up and fault conditions when FBX is close to SGND. used, an RT resistor should be chosen to program a switch- ing frequency 20% slower than SYNC pulse frequency.
GND:
Source Terminal of Switch and the GND Input to the Tie the SYNC pin to SGND if this feature is not used. This Switch Current Comparator. signal is ignored during FB frequency foldback or when
GNDK:
Kelvin Connection Pin between GND and SGND. INTVCC is less than 2.7V. Kelvin connect this pin to the SGND plane close to the IC.
V
See the Board Layout section.
IN:
Supply Pin for Internal Leads and the VIN LDO Regu- lator of INTVCC. Must be locally bypassed to GND with a
INTVCC:
Regulated Supply for Internal Loads and Gate minimum of 1µF capacitor placed close to this pin. Driver. Regulated to 4.75V if powered from DRIVE or
V
regulated to 3.75V if powered from V
C:
Error Amplifier Compensation Pin. Used to stabilize IN. The INTVCC pin the voltage loop with an external RC network. Place com- must be bypassed to SGND with a minimum of 4.7µF pensation components between the V capacitor placed close to the pin. C pin and SGND. 3959fa For more information www.linear.com/LT3959 7 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Applications Information Typical Applications Package Description Revision History Related Parts