Datasheet LT3473, LT3473A (Analog Devices) - 10
| Hersteller | Analog Devices |
| Beschreibung | Micropower 1A Boost Converter with Schottky and Output Disconnect |
| Seiten / Seite | 12 / 10 — APPLICATIO S I FOR ATIO. Thermal Shutdown. Auxiliary NPN Devices (LT3473A … |
| Dateiformat / Größe | PDF / 276 Kb |
| Dokumentensprache | Englisch |
APPLICATIO S I FOR ATIO. Thermal Shutdown. Auxiliary NPN Devices (LT3473A Only). Board Layout Consideration
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LT3473/LT3473A
U U W U APPLICATIO S I FOR ATIO
between the OUT pin and ground. A ceramic capacitor with connected to the two bases as shown in Figure 5 to a value of 1µF is a good choice. The voltage drop (PNP generate buffered voltage at the emitters. When sourcing VCESAT) can be accounted for by setting the output voltage high current at low voltage, keep in mind that the NPNs according to the following formula: will be dissipating a fair amount of power, which must be supplied by the DC/DC converter. ⎛ R2⎞ V = V – V = V • ⎜1+ – V OUT INT CESAT REF ⎟ CESAT ⎝ R ⎠ 1
Thermal Shutdown
The LT3473 has thermal shutdown circuitry that shuts down
Auxiliary NPN Devices (LT3473A Only)
the part when the junction temperature reaches approxi- The LT3473A has two auxiliary NPNs as shown in the mately 145°C to protect the part from abnormal operation Block Diagram that can provide intermediate outputs less with high power dissipation, such as an output short cir- than OUT. The collectors of the NPNs are connected to the cuit or excessive power dissipation in the auxiliary NPNs. OUT pin internally. Each NPN can dissipate 100mW safely The part will turn back on when the junction cools down to and has a minimum beta of 60. A resistor string can be approximately 125°C. If the abnormal condition remains, the part will turn on and off while maintaining the junction temperature within the window between 125°C and 145°C. 2 OUT REXT1
Board Layout Consideration
3 NB1 As with all switching regulators, careful attention must be 4 paid to the PCB board layout and component placement. REXT2 NE1 To maximize efficiency, switch rise and fall times are made 5 NB2 as short as possible. To prevent electromagnetic interfer- R ence (EMI) problems, proper layout of the high frequency EXT3 6 NE2 switching path is essential. The voltage signal of the SW 3473 F05 pin has sharp rise and fall edges. Minimize the length and
Figure 5. Auxiliary NPN Transistors in LT3473A. REXT1, REXT2
area of all traces connected to the SW pin and always use
and REXT3 Set Intermediate Voltage at NE1 and NE2
a ground plane under the switching regulator to minimize interplane coupling. Recommended component place- ment is shown in Figure 6. OUT 1 12 2 11 OUT 3 10 13 1 8 4 9 2 7 5 8 9 3 6 6 7 4 5 3473 F06b 3473 F06a
Figure 6. Recommended Component Placement
3473f 10
U U W U APPLICATIO S I FOR ATIO
between the OUT pin and ground. A ceramic capacitor with connected to the two bases as shown in Figure 5 to a value of 1µF is a good choice. The voltage drop (PNP generate buffered voltage at the emitters. When sourcing VCESAT) can be accounted for by setting the output voltage high current at low voltage, keep in mind that the NPNs according to the following formula: will be dissipating a fair amount of power, which must be supplied by the DC/DC converter. ⎛ R2⎞ V = V – V = V • ⎜1+ – V OUT INT CESAT REF ⎟ CESAT ⎝ R ⎠ 1
Thermal Shutdown
The LT3473 has thermal shutdown circuitry that shuts down
Auxiliary NPN Devices (LT3473A Only)
the part when the junction temperature reaches approxi- The LT3473A has two auxiliary NPNs as shown in the mately 145°C to protect the part from abnormal operation Block Diagram that can provide intermediate outputs less with high power dissipation, such as an output short cir- than OUT. The collectors of the NPNs are connected to the cuit or excessive power dissipation in the auxiliary NPNs. OUT pin internally. Each NPN can dissipate 100mW safely The part will turn back on when the junction cools down to and has a minimum beta of 60. A resistor string can be approximately 125°C. If the abnormal condition remains, the part will turn on and off while maintaining the junction temperature within the window between 125°C and 145°C. 2 OUT REXT1
Board Layout Consideration
3 NB1 As with all switching regulators, careful attention must be 4 paid to the PCB board layout and component placement. REXT2 NE1 To maximize efficiency, switch rise and fall times are made 5 NB2 as short as possible. To prevent electromagnetic interfer- R ence (EMI) problems, proper layout of the high frequency EXT3 6 NE2 switching path is essential. The voltage signal of the SW 3473 F05 pin has sharp rise and fall edges. Minimize the length and
Figure 5. Auxiliary NPN Transistors in LT3473A. REXT1, REXT2
area of all traces connected to the SW pin and always use
and REXT3 Set Intermediate Voltage at NE1 and NE2
a ground plane under the switching regulator to minimize interplane coupling. Recommended component place- ment is shown in Figure 6. OUT 1 12 2 11 OUT 3 10 13 1 8 4 9 2 7 5 8 9 3 6 6 7 4 5 3473 F06b 3473 F06a
Figure 6. Recommended Component Placement
3473f 10