Datasheet LT3471 (Analog Devices) - 7

LT3471
APPLICATIONS INFORMATION Soft-Start and Shutdown Features CAPACITOR SELECTION
To shut down the part, ground both SHDN/SS pins. To Low ESR (equivalent series resistance) capacitors should shut down one switcher but not the other one, ground that be used at the output to minimize the output ripple voltage. switcher’s SHDN/SS pin. The soft-start feature provides a Multi-layer ceramic capacitors are an excellent choice, way to limit the inrush current drawn from the supply upon as they have extremely low ESR and are available in very start-up. To use the soft-start feature for either switcher, small packages. X5R dielectrics are preferred, followed slowly ramp up that switcher’s SHDN/SS pin. The rate of by X7R, as these materials retain the capacitance over voltage rise at the output of the switcher’s comparator (A1 wide voltage and temperature ranges. A 4.7μF to 15μF or A3 for switcher 1 or switcher 2 respectively) tracks the output capacitor is suffi cient for most applications, but rate of voltage rise at the SHDN/SS pin once the SHDN/SS systems with very low output currents may need only a pin has reached about 1.1V. The soft-start function will 1μF or 2.2μF output capacitor. Solid tantalum or OS-CON go away once the voltage at the SHDN/SS pin exceeds capacitors can be used, but they will occupy more board 1.8V. See the Peak Switch Current vs SHDN/SS Voltage area than a ceramic and will have a higher ESR. Always graph in the Typical Performance Characteristics section. use a capacitor with a suffi cient voltage rating. The rate of voltage rise at the SHDN/SS pin can easily be Ceramic capacitors also make a good choice for the input controlled with a simple RC network connected between decoupling capacitor, which should be placed as close as the control signal and the SHDN/SS pin. Typical values possible to the LT3471. A 4.7μF to 10μF input capacitor for the RC network are 4.7kΩ and 0.33μF, giving start-up is suffi cient for most applications. Table 2 shows a list times on the order of milliseconds. This RC time constant of several ceramic capacitor manufacturers. Consult the can be adjusted to give different start-up times. If differ- manufacturers for detailed information on their entire ent values of resistance are to be used, keep in mind the SHDN selection of ceramic parts. /SS Current vs SHDN/SS voltage graph along with the Peak Switch Current vs SHDN/SS Voltage graph, both
Table 2. Ceramic Capacitor Manufacturers
found in the Typical Performance Characteristics section. Taiyo Yuden (408) 573-4150 www.t-yuden.com The impedance looking into the SHDN/SS pin depends AVX (803) 448-9411 www.avxcorp.com on whether the SHDN/SS is above or below VIN. Normally Murata (714) 852-2001 www.murata.com SHDN/SS will not be driven above VIN, and thus the imped- The decision to use either low ESR (ceramic) capacitors ance looks like 100kΩ in series with a diode. If the voltage or the higher ESR (tantalum or OS-CON) capacitors can of the SHDN/SS pin is above VIN, the impedance looks affect the stability of the overall system. The ESR of any more like 50kΩ in series with a diode. This 100kΩ or 50kΩ capacitor, along with the capacitance itself, contributes impedance can have a slight effect on the start-up time if a zero to the system. For the tantalum and OS-CON ca- you choose the R in the RC soft-start network too large. pacitors, this zero is located at a lower frequency due to Another consideration is selecting the soft-start time so the higher value of the ESR, while the zero of a ceramic that the soft-start feature is dominated by the RC network capacitor is at a much higher frequency and can generally and not the capacitor on VREF. (See VREF voltage reference be ignored. section of the Applications Information for details.) A phase lead zero can be intentionally introduced by placing The soft-start feature is of particular importance in ap- a capacitor (C plications where the switch will see voltage levels of 30V PL) in parallel with the resistor (R3) between V or higher. In these applications, the simultaneous presence OUT and VFB as shown in Figure 2. The frequency of the zero is determined by the following equation. of high current and voltage during startup may cause an overstress condition to the switch. Therefore, depending 1 ƒ on input and output voltage conditions, higher RC time Z = 2π •R3 • CPL constant values may be necessary to improve the rug- gedness of the design. 3471fb 7