Datasheet LT1945 (Analog Devices) - 4
| Hersteller | Analog Devices |
| Beschreibung | Dual Micropower DC/DC Converter with Positive and Negative Outputs |
| Seiten / Seite | 8 / 4 — PIN FUNCTIONS. NFB1 (Pin 1):. SW2 (Pin 6):. SHDN1. (Pin 2):. PGND (Pins … |
| Dateiformat / Größe | PDF / 129 Kb |
| Dokumentensprache | Englisch |
PIN FUNCTIONS. NFB1 (Pin 1):. SW2 (Pin 6):. SHDN1. (Pin 2):. PGND (Pins 7, 9):. GND (Pin 3):. VIN (Pin 8):. SHDN2 (Pin 4):. SW1 (Pin 10):
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LT1945
PIN FUNCTIONS NFB1 (Pin 1):
Feedback Pin for Switcher 1. Set the output
SW2 (Pin 6):
Switch Pin for Switcher 2. This is the voltage by selecting values for R1 and R2. collector of the internal NPN power switch. Minimize the
SHDN1
metal trace area connected to the pin to minimize EMI.
(Pin 2):
Shutdown Pin for Switcher 1. Tie this pin to 0.9V or higher to enable device. Tie below 0.25V
PGND (Pins 7, 9):
Power Ground. Tie these pins directly to turn it off. to the local ground plane. Both pins must be tied.
GND (Pin 3):
Ground. Tie this pin directly to the local
VIN (Pin 8):
Input Supply Pin. Bypass this pin with a ground plane. capacitor as close to the device as possible.
SHDN2 (Pin 4):
Shutdown Pin for Switcher 2. Tie this
SW1 (Pin 10):
Switch Pin for Switcher 1. This is the pin to 0.9V or higher to enable device. Tie below 0.25V collector of the internal NPN power switch. Minimize the to turn it off. metal trace area connected to the pin to minimize EMI.
FB2 (Pin 5):
Feedback Pin for Switcher 2. Set the output voltage by selecting values for R1B and R2B.
BLOCK DIAGRAM
C3 D2 L1 L2 L3 V V IN OUT1 VOUT2 VIN D1 C2 C1 C4 VIN SHDN1 SW1 SW2 SHDN2 8 2 10 6 4 VIN R5 R6 R6B R5B 80k 80k 40k 40k A1 A1B + + ENABLE ENABLE VOUT2 – – Q1B R1B Q1 (EXTERNAL) Q2 400ns 400ns Q2B FB2 Q3 Q3B 5 X10 ONE-SHOT ONE-SHOT X10 DRIVER R2B DRIVER R3 (EXTERNAL) RESET RESET R3B 60k 30k + + R4 R4B V 0.12Ω 0.12Ω OUT1 280k 140k – 42mV 42mV – A2 R1 A2B (EXTERNAL) NFB1 1 SWITCHER 1 SWITCHER 2 R2 GND PGND PGND (EXTERNAL) 3 9 7 1945 BD
Figure 1. LT1945 Block Diagram OPERATION
The LT1945 uses a constant off-time control scheme slightly below –1.23V, comparator A1 disables most of to provide high effi ciencies over a wide range of output the internal circuitry. Output current is then provided by current. Operation can be best understood by referring capacitor C2, which slowly discharges until the voltage to the block diagram in Figure 1. Q1 and Q2 along with at the NFB1 pin goes above the hysteresis point of A1 R3 and R4 form a bandgap reference used to regulate (typical hysteresis at the NFB1 pin is 8mV). A1 then enables the output voltage. When the voltage at the NFB1 pin is the internal circuitry, turns on power switch Q3, and the 1945fa 4
PIN FUNCTIONS NFB1 (Pin 1):
Feedback Pin for Switcher 1. Set the output
SW2 (Pin 6):
Switch Pin for Switcher 2. This is the voltage by selecting values for R1 and R2. collector of the internal NPN power switch. Minimize the
SHDN1
metal trace area connected to the pin to minimize EMI.
(Pin 2):
Shutdown Pin for Switcher 1. Tie this pin to 0.9V or higher to enable device. Tie below 0.25V
PGND (Pins 7, 9):
Power Ground. Tie these pins directly to turn it off. to the local ground plane. Both pins must be tied.
GND (Pin 3):
Ground. Tie this pin directly to the local
VIN (Pin 8):
Input Supply Pin. Bypass this pin with a ground plane. capacitor as close to the device as possible.
SHDN2 (Pin 4):
Shutdown Pin for Switcher 2. Tie this
SW1 (Pin 10):
Switch Pin for Switcher 1. This is the pin to 0.9V or higher to enable device. Tie below 0.25V collector of the internal NPN power switch. Minimize the to turn it off. metal trace area connected to the pin to minimize EMI.
FB2 (Pin 5):
Feedback Pin for Switcher 2. Set the output voltage by selecting values for R1B and R2B.
BLOCK DIAGRAM
C3 D2 L1 L2 L3 V V IN OUT1 VOUT2 VIN D1 C2 C1 C4 VIN SHDN1 SW1 SW2 SHDN2 8 2 10 6 4 VIN R5 R6 R6B R5B 80k 80k 40k 40k A1 A1B + + ENABLE ENABLE VOUT2 – – Q1B R1B Q1 (EXTERNAL) Q2 400ns 400ns Q2B FB2 Q3 Q3B 5 X10 ONE-SHOT ONE-SHOT X10 DRIVER R2B DRIVER R3 (EXTERNAL) RESET RESET R3B 60k 30k + + R4 R4B V 0.12Ω 0.12Ω OUT1 280k 140k – 42mV 42mV – A2 R1 A2B (EXTERNAL) NFB1 1 SWITCHER 1 SWITCHER 2 R2 GND PGND PGND (EXTERNAL) 3 9 7 1945 BD
Figure 1. LT1945 Block Diagram OPERATION
The LT1945 uses a constant off-time control scheme slightly below –1.23V, comparator A1 disables most of to provide high effi ciencies over a wide range of output the internal circuitry. Output current is then provided by current. Operation can be best understood by referring capacitor C2, which slowly discharges until the voltage to the block diagram in Figure 1. Q1 and Q2 along with at the NFB1 pin goes above the hysteresis point of A1 R3 and R4 form a bandgap reference used to regulate (typical hysteresis at the NFB1 pin is 8mV). A1 then enables the output voltage. When the voltage at the NFB1 pin is the internal circuitry, turns on power switch Q3, and the 1945fa 4