Datasheet LT1534 (Analog Devices) - 9

LT1534/LT1534-1
U U W U APPLICATIONS INFORMATION
If the FB pin is below 0.4V the oscillator discharge time will Usually it will be desirable to keep the voltage and current increase, causing the oscillation frequency to decrease by slew resistors approximately the same. There are circum- approximately 6:1. This feature helps minimize power stances where a better optimization can be found by dissipation during start-up and short-circuit conditions. adjusting each separately, but as these values are sepa- rated further, a loss of independence of control will occur. Oscillator frequency is important for noise reduction in two ways: 1) the lower the oscillator frequency the lower Starting from the lowest resistor setting adjust the pots the harmonics of waveforms are, making it easier to filter until the noise level meets your guidelines. Note that them, 2) the oscillator will control the placement of output slower slewing waveforms will dissipate more power so frequency harmonics which can aid in specific problems that efficiency will drop. You can also monitor this as you where you might be trying to avoid a certain frequency make your slew adjustment. bandwidth that is used for detection elsewhere. It is possible to use a single slew setting resistor. In this case the R
Oscillator Sync
VSL and RCSL pins are tied together. A resistor with a value of 2k to 34k (one half the individual resistors) If a more precise frequency is desired (e.g., to accurately can then be tied from these pins to ground. place harmonics) the oscillator can be synchronized to an external clock. Set the RC timing components for an
Emitter Inductance
oscillator frequency 10% lower than the desired sync A small inductance in the power ground minimizes a frequency. potential dip in the output current falling edge that can Drive the SYNC pin with a square wave (with greater than occur under fast slewing, 25nH is usually sufficient. Greater 1.4V amplitude). The rising edge of the sync square wave than 50nH may produce unwanted oscillations in the will initiate clock discharge. The sync pulse should have a voltage output. The inductance can be created by wire or minimum of 0.5µs pulse width. board trace with the equivalent of one inch of straight length. A spiral board trace will require less length. Be careful in synchronizing to frequencies much different from the part since the internal oscillator charge slope
Positive Output Voltage Setting
determines slope compensation. It would be possible to get into subharmonic oscillation if the sync doesn’t allow Sensing of a positive output voltage is usually done using for the charge cycle of the capacitor to initiate slope a resistor divider from the output to the FB pin. The compensation. In general, this will not be a problem until positive input to the error amp is connected internally to a the sync frequency is greater than 1.5 times the oscillator 1.25V bandgap reference. The FB pin will regulate to this free-run frequency. voltage. R1 FB PIN VOUT
Slew Rate Setting
R2 Setting the voltage and current slew rates is easy. External 1534 F01 resistors to ground on the RVSL and RCSL pins determine the slew rates. Determining what slew rate to use is more
Figure 2
difficult. There are several ways to approach the problem. Referring to Figure 2, R1 is determined by: First start by putting a 50k resistor pot with a 3.9k series resistance on each pin. In general, the next step will be to  V  monitor the noise that you are concerned with. Be careful R = R OUT 1 2 − 1 in measurement technique (consult AN70). Keep probe  1 25  . ground leads very short. The FB bias current represents a small error and can usually be ignored for values of R1|| R2 up to 10k. 9