Datasheet LT1372, LT1377 (Analog Devices) - 10
| Hersteller | Analog Devices |
| Beschreibung | 500kHz and 1MHz High Efficiency 1.5A Switching Regulators |
| Seiten / Seite | 12 / 10 — APPLICATIO S I FOR ATIO. Frequency Compensation. Figure 3. More Help. … |
| Dateiformat / Größe | PDF / 203 Kb |
| Dokumentensprache | Englisch |
APPLICATIO S I FOR ATIO. Frequency Compensation. Figure 3. More Help. Switch Node Considerations
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LT1372/LT1377
U U W U APPLICATIO S I FOR ATIO Frequency Compensation
(magnetic) radiation is minimized by keeping output di- ode, switch pin, and output bypass capacitor leads as Loop frequency compensation is performed on the output short as possible. E field radiation is kept low by minimiz- of the error amplifier (VC pin) with a series RC network. ing the length and area of all traces connected to the switch The main pole is formed by the series capacitor and the pin. A ground plane should always be used under the output impedance (≈500kΩ) of the error amplifier. The switcher circuitry to prevent interplane coupling. pole falls in the range of 2Hz to 20Hz. The series resistor creates a “zero” at 1kHz to 5kHz, which improves loop The high speed switching current path is shown schemati- stability and transient response. A second capacitor, cally in Figure 3. Minimum lead length in this path is typically one-tenth the size of the main compensation essential to ensure clean switching and low EMI. The path capacitor, is sometimes used to reduce the switching including the switch, output diode, and output capacitor is frequency ripple on the V the only one containing nanosecond rise and fall times. C pin. VC pin ripple is caused by output voltage ripple attenuated by the output divider and Keep this path as short as possible. multiplied by the error amplifier. Without the second SWITCH L1 capacitor, V NODE C pin ripple is: VOUT 1.245(VRIPPLE)(gm)(RC) HIGH VC Pin Ripple = V (V IN FREQUENCY LOAD OUT) CIRCULATING PATH VRIPPLE = Output ripple (VP–P) gm = Error amplifier transconductance (≈1500µmho) LT1372 • F03 R
Figure 3
C = Series resistor on VC pin VOUT = DC output voltage
More Help
To prevent irregular switching, V For more detailed information on switching regulator C pin ripple should be kept below 50mV circuits, please see Application Note 19. Linear Technol- P–P. Worst-case VC pin ripple occurs at maximum output load current and will also be increased ogy also offers a computer software program, SwitcherCAD, if poor quality (high ESR) output capacitors are used. The to assist in designing switching converters. In addition, addition of a 0.0047µF capacitor on the V our applications department is always ready to lend a C pin reduces switching frequency ripple to only a few millivolts. A low helping hand. value for RC will also reduce VC pin ripple, but loop phase margin may be inadequate.
Switch Node Considerations
For maximum efficiency, switch rise and fall time are made as short as possible. To prevent radiation and high frequency resonance problems, proper layout of the com- ponents connected to the switch node is essential. B field 10
U U W U APPLICATIO S I FOR ATIO Frequency Compensation
(magnetic) radiation is minimized by keeping output di- ode, switch pin, and output bypass capacitor leads as Loop frequency compensation is performed on the output short as possible. E field radiation is kept low by minimiz- of the error amplifier (VC pin) with a series RC network. ing the length and area of all traces connected to the switch The main pole is formed by the series capacitor and the pin. A ground plane should always be used under the output impedance (≈500kΩ) of the error amplifier. The switcher circuitry to prevent interplane coupling. pole falls in the range of 2Hz to 20Hz. The series resistor creates a “zero” at 1kHz to 5kHz, which improves loop The high speed switching current path is shown schemati- stability and transient response. A second capacitor, cally in Figure 3. Minimum lead length in this path is typically one-tenth the size of the main compensation essential to ensure clean switching and low EMI. The path capacitor, is sometimes used to reduce the switching including the switch, output diode, and output capacitor is frequency ripple on the V the only one containing nanosecond rise and fall times. C pin. VC pin ripple is caused by output voltage ripple attenuated by the output divider and Keep this path as short as possible. multiplied by the error amplifier. Without the second SWITCH L1 capacitor, V NODE C pin ripple is: VOUT 1.245(VRIPPLE)(gm)(RC) HIGH VC Pin Ripple = V (V IN FREQUENCY LOAD OUT) CIRCULATING PATH VRIPPLE = Output ripple (VP–P) gm = Error amplifier transconductance (≈1500µmho) LT1372 • F03 R
Figure 3
C = Series resistor on VC pin VOUT = DC output voltage
More Help
To prevent irregular switching, V For more detailed information on switching regulator C pin ripple should be kept below 50mV circuits, please see Application Note 19. Linear Technol- P–P. Worst-case VC pin ripple occurs at maximum output load current and will also be increased ogy also offers a computer software program, SwitcherCAD, if poor quality (high ESR) output capacitors are used. The to assist in designing switching converters. In addition, addition of a 0.0047µF capacitor on the V our applications department is always ready to lend a C pin reduces switching frequency ripple to only a few millivolts. A low helping hand. value for RC will also reduce VC pin ripple, but loop phase margin may be inadequate.
Switch Node Considerations
For maximum efficiency, switch rise and fall time are made as short as possible. To prevent radiation and high frequency resonance problems, proper layout of the com- ponents connected to the switch node is essential. B field 10