Datasheet LT1372, LT1377 (Analog Devices) - 5
| Hersteller | Analog Devices |
| Beschreibung | 500kHz and 1MHz High Efficiency 1.5A Switching Regulators |
| Seiten / Seite | 12 / 5 — PI FU CTIO S. VC (Pin 1):. VIN (Pin 5):. GND S (Pin 6):. FB (Pin 2):. GND … |
| Dateiformat / Größe | PDF / 203 Kb |
| Dokumentensprache | Englisch |
PI FU CTIO S. VC (Pin 1):. VIN (Pin 5):. GND S (Pin 6):. FB (Pin 2):. GND (Pin 7):. NFB (Pin 3):. SW (Pin 8):. S/S (Pin 4):. BLOCK DIAGRA
Modelllinie für dieses Datenblatt
Textversion des Dokuments
LT1372/LT1377
U U U PI FU CTIO S VC (Pin 1):
The compensation pin is used for frequency
VIN (Pin 5):
Bypass input supply pin with 10µF or more. The compensation, current limiting and soft start. It is the part goes into undervoltage lockout when VIN drops below output of the error amplifier and the input of the current 2.5V. Undervoltage lockout stops switching and pulls the comparator. Loop frequency compensation can be per- VC pin low. formed with an RC network connected from the VC pin to
GND S (Pin 6):
The ground sense pin is a “clean” ground. ground. The internal reference, error amplifier and negative feed-
FB (Pin 2):
The feedback pin is used for positive output back amplifier are referred to the ground sense pin. Con- voltage sensing and oscillator frequency shifting. It is the nect it to ground. Keep the ground path connection to the inverting input to the error amplifier. The noninverting output resistor divider and the VC compensation network input of this amplifier is internally tied to a 1.245V free of large ground currents. reference. Load on the FB pin should not exceed 250µA
GND (Pin 7):
The ground pin is the emitter connection of when the NFB pin is used. See Applications Information. the power switch and has large currents flowing through it.
NFB (Pin 3):
The negative feedback pin is used for negative It should be connected directly to a good quality ground output voltage sensing. It is connected to the inverting plane. input of the negative feedback amplifier through a 100k
V
source resistor.
SW (Pin 8):
The switch pin is the collector of the power switch and has large currents flowing through it. Keep the
S/S (Pin 4):
Shutdown and Synchronization Pin. The S/S traces to the switching components as short as possible to pin is logic level compatible. Shutdown is active low and minimize radiation and voltage spikes. the shutdown threshold is typically 1.3V. For normal operation, pull the S/S pin high, tie it to VIN or leave it floating. To synchronize switching, drive the S/S pin be- tween 600kHz and 800kHz (LT1372) or 1.2MHz to 1.6MHz (LT1377).
W BLOCK DIAGRA
VIN SW SHUTDOWN LOW DROPOUT S/S ANTI-SAT DELAY AND RESET 2.3V REG SYNC OSC LOGIC DRIVER SWITCH 5:1 FREQUENCY SHIFT + NFBA 100k NFB – 50k COMP – FB + EA IA 0.08Ω + – V A C V ≈ 6 1.245V REF GND LT1372 • BD GND SENSE 5
U U U PI FU CTIO S VC (Pin 1):
The compensation pin is used for frequency
VIN (Pin 5):
Bypass input supply pin with 10µF or more. The compensation, current limiting and soft start. It is the part goes into undervoltage lockout when VIN drops below output of the error amplifier and the input of the current 2.5V. Undervoltage lockout stops switching and pulls the comparator. Loop frequency compensation can be per- VC pin low. formed with an RC network connected from the VC pin to
GND S (Pin 6):
The ground sense pin is a “clean” ground. ground. The internal reference, error amplifier and negative feed-
FB (Pin 2):
The feedback pin is used for positive output back amplifier are referred to the ground sense pin. Con- voltage sensing and oscillator frequency shifting. It is the nect it to ground. Keep the ground path connection to the inverting input to the error amplifier. The noninverting output resistor divider and the VC compensation network input of this amplifier is internally tied to a 1.245V free of large ground currents. reference. Load on the FB pin should not exceed 250µA
GND (Pin 7):
The ground pin is the emitter connection of when the NFB pin is used. See Applications Information. the power switch and has large currents flowing through it.
NFB (Pin 3):
The negative feedback pin is used for negative It should be connected directly to a good quality ground output voltage sensing. It is connected to the inverting plane. input of the negative feedback amplifier through a 100k
V
source resistor.
SW (Pin 8):
The switch pin is the collector of the power switch and has large currents flowing through it. Keep the
S/S (Pin 4):
Shutdown and Synchronization Pin. The S/S traces to the switching components as short as possible to pin is logic level compatible. Shutdown is active low and minimize radiation and voltage spikes. the shutdown threshold is typically 1.3V. For normal operation, pull the S/S pin high, tie it to VIN or leave it floating. To synchronize switching, drive the S/S pin be- tween 600kHz and 800kHz (LT1372) or 1.2MHz to 1.6MHz (LT1377).
W BLOCK DIAGRA
VIN SW SHUTDOWN LOW DROPOUT S/S ANTI-SAT DELAY AND RESET 2.3V REG SYNC OSC LOGIC DRIVER SWITCH 5:1 FREQUENCY SHIFT + NFBA 100k NFB – 50k COMP – FB + EA IA 0.08Ω + – V A C V ≈ 6 1.245V REF GND LT1372 • BD GND SENSE 5