Datasheet LT1307, LT1307B (Analog Devices) - 7
| Hersteller | Analog Devices |
| Beschreibung | Single Cell Micropower 600kHz PWM DC/DC Converters |
| Seiten / Seite | 20 / 7 — PI FU CTIO S. VC (Pin 1):. SW (Pin 5):. VIN (Pin 6):. FB (Pin 2):. LBI … |
| Dateiformat / Größe | PDF / 383 Kb |
| Dokumentensprache | Englisch |
PI FU CTIO S. VC (Pin 1):. SW (Pin 5):. VIN (Pin 6):. FB (Pin 2):. LBI (Pin 7):. SHDN (Pin 3):. LBO (Pin 8):. GND (Pin 4):. BLOCK DIAGRA
Modelllinie für dieses Datenblatt
- LT1307BCMS8#PBF LT1307BCMS8#TRPBF LT1307BCS8#PBF LT1307BCS8#TRPBF LT1307BIS8#PBF LT1307BIS8#TRPBF LT1307CMS8#PBF LT1307CMS8#PBF LT1307CMS8#TRPBF LT1307CMS8#TRPBF LT1307CN8#PBF LT1307CN8#PBF LT1307CS8#PBF LT1307CS8#PBF LT1307CS8#TRPBF LT1307CS8#TRPBF LT1307IS8#PBF LT1307IS8#PBF LT1307IS8#TRPBF LT1307IS8#TRPBF
Textversion des Dokuments
LT1307/LT1307B
U U U PI FU CTIO S VC (Pin 1):
Compensation Pin for Error Amplifier. Con-
SW (Pin 5):
Switch Pin. Connect inductor/diode here. nect a series RC from this pin to ground. Typical values Minimize trace area at this pin to keep EMI down. are 100kΩ and 680pF. Minimize trace area at VC.
VIN (Pin 6):
Supply Pin. Must have 1µF ceramic bypass
FB (Pin 2):
Feedback Pin. Reference voltage is 1.22V. capacitor right at the pin, connected directly to ground. Connect resistor divider tap here. Minimize trace area at
LBI (Pin 7):
Low-Battery Detector Input. 200mV refer- FB. Set VOUT according to: VOUT = 1.22V(1 + R1/R2). ence. Voltage on LBI must stay between ground and
SHDN (Pin 3):
Shutdown. Ground this pin to turn off 700mV. switcher. Must be tied to VIN (or higher voltage) to enable
LBO (Pin 8):
Low-Battery Detector Output. Open collec- switcher. Do not float the SHDN pin. tor, can sink 10µA. A 1MΩ pull-up is recommended.
GND (Pin 4):
Ground. Connect directly to local ground plane.
W BLOCK DIAGRA
VIN 6 VIN R5 R6 40k 40k + SHDN VC SHUTDOWN 3 gm 1 VOUT – LBI R1 ERROR (EXTERNAL) + 7 + FB AMPLIFIER LBO Q1 Q2 FB 2 × * 10 ENABLE 8 R2 R3 BIAS – – A4 (EXTERNAL) A1 200mV 30k R4 140k COMPARATOR SW – 5 DRIVER FF RAMP GENERATOR + R Q Q3 + Σ S + A2 + A = 3 0.15Ω 600kHz OSCILLATOR – 4 *HYSTERESIS IN LT1307 ONLY GND 1307 F02
Figure 2. LT1307/LT1307B Block Diagram
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U U U PI FU CTIO S VC (Pin 1):
Compensation Pin for Error Amplifier. Con-
SW (Pin 5):
Switch Pin. Connect inductor/diode here. nect a series RC from this pin to ground. Typical values Minimize trace area at this pin to keep EMI down. are 100kΩ and 680pF. Minimize trace area at VC.
VIN (Pin 6):
Supply Pin. Must have 1µF ceramic bypass
FB (Pin 2):
Feedback Pin. Reference voltage is 1.22V. capacitor right at the pin, connected directly to ground. Connect resistor divider tap here. Minimize trace area at
LBI (Pin 7):
Low-Battery Detector Input. 200mV refer- FB. Set VOUT according to: VOUT = 1.22V(1 + R1/R2). ence. Voltage on LBI must stay between ground and
SHDN (Pin 3):
Shutdown. Ground this pin to turn off 700mV. switcher. Must be tied to VIN (or higher voltage) to enable
LBO (Pin 8):
Low-Battery Detector Output. Open collec- switcher. Do not float the SHDN pin. tor, can sink 10µA. A 1MΩ pull-up is recommended.
GND (Pin 4):
Ground. Connect directly to local ground plane.
W BLOCK DIAGRA
VIN 6 VIN R5 R6 40k 40k + SHDN VC SHUTDOWN 3 gm 1 VOUT – LBI R1 ERROR (EXTERNAL) + 7 + FB AMPLIFIER LBO Q1 Q2 FB 2 × * 10 ENABLE 8 R2 R3 BIAS – – A4 (EXTERNAL) A1 200mV 30k R4 140k COMPARATOR SW – 5 DRIVER FF RAMP GENERATOR + R Q Q3 + Σ S + A2 + A = 3 0.15Ω 600kHz OSCILLATOR – 4 *HYSTERESIS IN LT1307 ONLY GND 1307 F02
Figure 2. LT1307/LT1307B Block Diagram
1307fa 7