Datasheet LT3150 (Analog Devices) - 10

LT3150
U U W U APPLICATIO S I FOR ATIO
is low enough such that Q1 and Q2 do not saturate, even the COMP pin. The output impedance of the gm stage is when VIN1 is 1V. When there is no load, FB1 rises slightly about 1MΩ and thus, 84dB of typical DC error amplifier above 1.23V, causing VC (the error amplifier’s output) to open-loop gain is realized along with a typical 75MHz decrease. Comparator A2’s output stays high, keeping uncompensated unity-gain crossover frequency. Note switch Q3 in the off state. As increased output loading that the overall feedback loop’s DC gain decreases from causes the FB1 voltage to decrease, A1’s output increases. the gain provided by the error amplifier by the attenuation Switch current is regulated directly on a cycle-by-cycle factor in the resistor divider network which sets the DC basis by the VC node. The flip flop is set at the beginning output voltage. External access to the high impedance of each switch cycle, turning on the switch. When the gain node of the error amplifier permits typical loop summation of a signal representing switch current and a compensation to be accomplished with a series RC + C ramp generator (introduced to avoid subharmonic oscilla- network to ground. tions at duty factors greater than 50%) exceeds the VC A high speed, high current output stage buffers the COMP signal, comparator A2 changes state, resetting the flip flop node and drives up to 5000pF of “effective” MOSFET gate and turning off the switch. More power is delivered to the capacitance with almost no change in load transient per- output as switch current is increased. The output voltage, formance. The output stage delivers up to 50mA peak attenuated by external resistor divider R1 and R2, appears when slewing the MOSFET gate in response to load at the FB1 pin, closing the overall loop. Frequency com- current transients. The typical output impedance of the pensation is provided internally by RC and CC. Transient GATE pin is typically 2Ω. This pushes the pole due to the response can be optimized by the addition of a phase lead error amplifier output impedance and the MOSFET input capacitor CPL in parallel with R1 in applications where capacitance well beyond the loop crossover frequency. If large value or low ESR output capacitors are used. the capacitance of the MOSFET used is less than 1500pF, As the load current is decreased, the switch turns on for a it may be necessary to add a small value series gate shorter period each cycle. If the load current is further resistor of 2Ω to 10Ω. This gate resistor helps damp the decreased, the converter will skip cycles to maintain LC resonance created by the MOSFET gate’s lead induc- output voltage regulation. tance and input capacitance. In addition, the pole formed by this resistance and the MOSFET input capacitance can The linear regulator controller section of the LT3150 Block be fine tuned. Diagram consists of a simple feedback control loop and multiple protection functions. Examining the Block Dia- Because the MOSFET pass transistor is connected as a gram for the LT3150, a start-up circuit provides controlled source follower, the power path gain is much more predict- start-up, including the precision-trimmed bandgap refer- able than designs that employ a discrete PNP transistor as ence, and establishes all internal current and voltage the pass device. This is due to the significant production biasing. variations encountered with PNP Beta. MOSFETs are also very high speed devices which enhance the ability to pro- Reference voltage accuracy at the FB2 pin is specified as ± duce a stable wide bandwidth control loop. An additional 0.6% at room temperature and as ±1% over the full advantage of the follower topology is inherently good line operating temperature range. This places the LT3150 rejection. Input supply disturbances do not propagate among a select group of regulators with a very tightly through to the output. The feedback loop for a regulator specified reference voltage tolerance. The 1.21V reference circuit is completed by providing an error signal to the FB2 is tied to the noninverting input of the main error amplifier pin. A resistor divider network senses the output voltage in the feedback control loop. and sets the regulated DC bias point. In general, the LT3150 The error amplifier consists of a single high gain gm stage regulator feedback loop permits a loop crossover frequency with a transconductance equal to 15 millimhos. The on the order of 1MHz while maintaining good phase and gain inverting terminal is brought out as the FB2 pin. The gm margins. This unity-gain frequency is a factor of 20 to 30 stage provides differential-to-single ended conversion at times the bandwidth of currently implemented regulator 3150f 10