Datasheet LT1573 (Analog Devices) - 5

LT1573
U U U PI FU CTIO S FB
activated by applying a voltage > 1.3V to the SHDN pin. The
(Pin 1):
The feedback pin is the inverting input of the error amplifier. The noninverting input of the error ampli- output voltage will restart as soon as the SHDN pin is fier is internally connected to a 1.265V reference. The error pulled below the shutdown threshold. If the shutdown/ amplifier will servo the drive to the output transistor, Q reset function is not used, the pin should be grounded. The OUT in Figure 1, to force the voltage at the feedback pin to be voltage applied to the SHDN pin can be higher than the 1.265V. Output voltage is set by a resistor divider as input voltage. When the SHDN pin voltage is higher than shown in Figure 1. For adjustable devices an external 2V, the SHDN pin current increases and is limited by an resistor divider is used to set the output voltage. For fixed internal 20k resistor. voltage devices the resistor divider is internal and the top
GND (Pin 4):
Circuit Ground. of the resistor divider is connected to the VOUT pin.
DRIVE (Pin 5):
The DRIVE pin is connected to the collector
LATCH (Pin 2):
The LT1573 provides overcurrent protec- of the main drive transistor of the LT1573. This drive tion with a timed latch-off circuit. The latch-off time out is transistor sinks the base current of the external PNP triggered when the DRIVE pin is pulled below the satura- output transistor. A resistor is normally inserted between tion voltage of the drive transistor. The saturation voltage the base of the external PNP output transistor and the is a function of the drive current and is equal to approxi- DRIVE pin. This resistor is sized to allow the LT1573 to mately 130mV at 20mA rising to 780mV at 250mA (see sink the appropriate amount of base current for a given typical performance curves). The time out is set by the application and to activate the overcurrent latch in a fault latch charging current and the value of a capacitor con- condition. nected between the LATCH pin and ground. If the overcurrent condition persists at the end of the timing
VIN (Pin 6):
This pin provides power to all internal circuitry cycle the regulator will latch off until either the latch is reset of the LT1573 including bias, start-up, thermal limit, error or power is cycled off and back on. The latch can be reset amplifier and all overcurrent latch circuitry. by either pulling the SHDN pin high, pulling current out of
VOUT (Pin 7):
The VOUT pin is the input to comparator C1 the LATCH pin greater than latching current or grounding shown in Block Diagram. This pin is normally connected the LATCH pin. Exceeding the thermal limit temperature to the output. The comparator C1 is used to disable the will trigger the latch with no timing delay. Under normal overcurrent latch during start-up when the output transis- condition, the DC voltage at the LATCH pin is zero. When tor is saturated. For fixed voltage devices the top of the the system is latched off, the DC voltage at theLATCH pin internal resistor divider that sets the output voltage is is two VBE above ground. connected to this pin.
SHDN (Pin 3):
The SHDN pin has two functions. It can be
COMP (Pin 8):
A compensation network is inserted used to turn off the output voltage by disabling the drive to between the VOUT and COMP pins to obtain optimal the output transistor. It can also be used to reset the transient response. Under normal condition, the DC volt- current limit latch. The shutdown/reset functions are age of the COMP pin sits at one VBE above ground. sn1573 1573fas 5