Datasheet LTC1380, LTC1393 (Analog Devices) - 9
| Hersteller | Analog Devices |
| Beschreibung | Single-Ended 8-Channel/ Differential 4-Channel Analog Multiplexer with SMBus Interface |
| Seiten / Seite | 12 / 9 — APPLICATIONS INFORMATION. Table 1. LTC1380/LTC1393 Address Selection. … |
| Revision | LTC1380/LTC1393: Single-Ended 8-Channel/ Differential 4-Channel Analog Multiplexer with SMBus Interface Data Sheet |
| Dateiformat / Größe | PDF / 246 Kb |
| Dokumentensprache | Englisch |
APPLICATIONS INFORMATION. Table 1. LTC1380/LTC1393 Address Selection. LTC1380. LTC1393
Modelllinie für dieses Datenblatt
Textversion des Dokuments
LTC1380/LTC1393
U U W U APPLICATIONS INFORMATION Table 1. LTC1380/LTC1393 Address Selection
Both the LTC1380 and LTC1393 are compatible with the
A1 A0 LTC1380 LTC1393
Philips/Signetics I2C Bus interface. This 1V threshold for 0 0 90H 98H SCA and SDA should not pose an operational problem 0 1 92H 9AH with I2C applications. 1 0 94H 9CH The multiplexer switches are selected as shown in Table 2. 1 1 96H 9EH Both the LTC1380 and the LTC1393 have an enable bit SCL is the synchronizing clock generated by the host. SDA (EN). A Low disables all switches while a High enables the is the bidirectional data transfer between the host and the selected switch as programmed by bits C2, C1 and C0. A slave. The host initiates a start bit by dropping the SDA line stop bit after a successful send byte sequence for LTC1380/ from High to Low while the SCL is High. The stop bit is LTC1393 will disable all switches before the new selected initiated by changing the SDA line from Low to High while switch is connected. SCL is High. All address, command and acknowledge
Table 2. Multiplexer Control Bits Truth Table
signals must be valid and should not change while SCL is
LTC1380 D + – O LTC1393 DO , DO
High. The acknowledge bit signals to the host the accep-
EN C2 C1 C0 CHANNEL STATUS CHANNEL STATUS
tance of a correct address byte or the command byte. 0 X X X All Off All Off 1 0 0 0 S0 S0+, S0– At VCC supply above 2.7V, the SCL and SDA input thresh- 1 0 0 1 S1 old is typically 1V with an input hysteresis of 100mV. The 1 0 1 0 S2 S1+, S1– typical SCL and SDA lines have either a resistive or current 1 0 1 1 S3 source pull-up at the host. The LTC1380/LTC1393 have an open-drain NMOS transistor at the SDA pin to sink 3mA 1 1 0 0 S4 S2+, S2– below 0.4V during the slave acknowledge sequence. The 1 1 0 1 S5 address selection input A1 and A0 are TTL compatible at 1 1 1 0 S6 S3+, S3– V 1 1 1 1 S7 CC = 5V.
U TYPICAL APPLICATIONS Simplified LTC1393 Application
5V 1 16 SMBus 0.1 S0+ V µF 15k 15k CC HOST 2 15 S0 – SCL SCL 3 14 S1+ SDA SDA 4 13 4 DIFFERENTIAL S1– A0 5 LTC1393 12 ANALOG INPUTS S2+ A1 6 11 S2– GND 7 10 S3+ D – O DIFFERENTIAL 8 9 + ANALOG OUTPUTS S3– DO 1380/93 TA03 9
U U W U APPLICATIONS INFORMATION Table 1. LTC1380/LTC1393 Address Selection
Both the LTC1380 and LTC1393 are compatible with the
A1 A0 LTC1380 LTC1393
Philips/Signetics I2C Bus interface. This 1V threshold for 0 0 90H 98H SCA and SDA should not pose an operational problem 0 1 92H 9AH with I2C applications. 1 0 94H 9CH The multiplexer switches are selected as shown in Table 2. 1 1 96H 9EH Both the LTC1380 and the LTC1393 have an enable bit SCL is the synchronizing clock generated by the host. SDA (EN). A Low disables all switches while a High enables the is the bidirectional data transfer between the host and the selected switch as programmed by bits C2, C1 and C0. A slave. The host initiates a start bit by dropping the SDA line stop bit after a successful send byte sequence for LTC1380/ from High to Low while the SCL is High. The stop bit is LTC1393 will disable all switches before the new selected initiated by changing the SDA line from Low to High while switch is connected. SCL is High. All address, command and acknowledge
Table 2. Multiplexer Control Bits Truth Table
signals must be valid and should not change while SCL is
LTC1380 D + – O LTC1393 DO , DO
High. The acknowledge bit signals to the host the accep-
EN C2 C1 C0 CHANNEL STATUS CHANNEL STATUS
tance of a correct address byte or the command byte. 0 X X X All Off All Off 1 0 0 0 S0 S0+, S0– At VCC supply above 2.7V, the SCL and SDA input thresh- 1 0 0 1 S1 old is typically 1V with an input hysteresis of 100mV. The 1 0 1 0 S2 S1+, S1– typical SCL and SDA lines have either a resistive or current 1 0 1 1 S3 source pull-up at the host. The LTC1380/LTC1393 have an open-drain NMOS transistor at the SDA pin to sink 3mA 1 1 0 0 S4 S2+, S2– below 0.4V during the slave acknowledge sequence. The 1 1 0 1 S5 address selection input A1 and A0 are TTL compatible at 1 1 1 0 S6 S3+, S3– V 1 1 1 1 S7 CC = 5V.
U TYPICAL APPLICATIONS Simplified LTC1393 Application
5V 1 16 SMBus 0.1 S0+ V µF 15k 15k CC HOST 2 15 S0 – SCL SCL 3 14 S1+ SDA SDA 4 13 4 DIFFERENTIAL S1– A0 5 LTC1393 12 ANALOG INPUTS S2+ A1 6 11 S2– GND 7 10 S3+ D – O DIFFERENTIAL 8 9 + ANALOG OUTPUTS S3– DO 1380/93 TA03 9