Datasheet LTM9008-14, LTM9007-14, LTM9006-14 (Analog Devices) - 9
| Hersteller | Analog Devices |
| Beschreibung | 14-Bit, 65Msps Low Power Octal ADCs |
| Seiten / Seite | 38 / 9 — TIMING DIAGRAMS. 2-Lane Output Mode, 12-Bit Serialization. 1-Lane Output … |
| Dateiformat / Größe | PDF / 1.1 Mb |
| Dokumentensprache | Englisch |
TIMING DIAGRAMS. 2-Lane Output Mode, 12-Bit Serialization. 1-Lane Output Mode, 16-Bit Serialization
Modelllinie für dieses Datenblatt
Textversion des Dokuments
LTM9008-14/ LTM9007-14/LTM9006-14
TIMING DIAGRAMS 2-Lane Output Mode, 12-Bit Serialization
tAP ANALOG N N+1 INPUT tENCH tENCL ENC– ENC+ t DCO– SER DCO+ tFRAME tDATA tSER FR+ FR– tPD tSER OUT#A– D9 D7 D5 D3 D13 D11 D9 D7 D5 D3 D13 D11 D9 OUT#A+ OUT#B– D8 D6 D4 D2 D12 D10 D8 D6 D4 D2 D12 D10 D8 OUT#B+ SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 90067814 TD03
1-Lane Output Mode, 16-Bit Serialization
tAP ANALOG N+1 N INPUT tENCH tENCL ENC– ENC+ t DCO– SER DCO+ tFRAME tDATA tSER FR– FR+ tPD tSER OUT#A– D1 D0 0 0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 D13 D12 D11 D10 OUT#A+ 90067814 TD04 SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 OUT#B+, OUT#B– ARE DISABLED
1-Lane Output Mode, 14-Bit Serialization
tAP ANALOG N+1 N INPUT tENCH tENCL ENC– ENC+ t DCO– SER DCO+ tFRAME tDATA tSER FR– FR+ tPD tSER OUT#A– D3 D2 D1 D0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D13 D12 D11 D10 OUT#A+ SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 90067814 TD06 OUT#B+, OUT#B– ARE DISABLED 90067814fb For more information www.linear.com/LTM9008-14 9 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs And Outputs Power Requirements Timing Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Pin Configuration Table Functional Block Diagram Applications Information Package Description Related Parts
TIMING DIAGRAMS 2-Lane Output Mode, 12-Bit Serialization
tAP ANALOG N N+1 INPUT tENCH tENCL ENC– ENC+ t DCO– SER DCO+ tFRAME tDATA tSER FR+ FR– tPD tSER OUT#A– D9 D7 D5 D3 D13 D11 D9 D7 D5 D3 D13 D11 D9 OUT#A+ OUT#B– D8 D6 D4 D2 D12 D10 D8 D6 D4 D2 D12 D10 D8 OUT#B+ SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 90067814 TD03
1-Lane Output Mode, 16-Bit Serialization
tAP ANALOG N+1 N INPUT tENCH tENCL ENC– ENC+ t DCO– SER DCO+ tFRAME tDATA tSER FR– FR+ tPD tSER OUT#A– D1 D0 0 0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 D13 D12 D11 D10 OUT#A+ 90067814 TD04 SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 OUT#B+, OUT#B– ARE DISABLED
1-Lane Output Mode, 14-Bit Serialization
tAP ANALOG N+1 N INPUT tENCH tENCL ENC– ENC+ t DCO– SER DCO+ tFRAME tDATA tSER FR– FR+ tPD tSER OUT#A– D3 D2 D1 D0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D13 D12 D11 D10 OUT#A+ SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 90067814 TD06 OUT#B+, OUT#B– ARE DISABLED 90067814fb For more information www.linear.com/LTM9008-14 9 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs And Outputs Power Requirements Timing Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Pin Configuration Table Functional Block Diagram Applications Information Package Description Related Parts