Datasheet LTM9002 (Analog Devices) - 7
| Hersteller | Analog Devices |
| Beschreibung | 14-Bit, 125Msps Dual-Channel IF/Baseband Receiver Subsystem |
| Seiten / Seite | 28 / 7 — TIMING DIAGRAMS. Dual Digital Output Bus Timing. Multiplexed Digital … |
| Dateiformat / Größe | PDF / 355 Kb |
| Dokumentensprache | Englisch |
TIMING DIAGRAMS. Dual Digital Output Bus Timing. Multiplexed Digital Output Bus Timing
Modelllinie für dieses Datenblatt
Textversion des Dokuments
LTM9002
TIMING DIAGRAMS Dual Digital Output Bus Timing
tAP N + 2 N + 4 ANALOG N INPUT N + 1 N + 3 N + 5 tH tL CLKA = CLKB tD D0-D13, OF N – 5 N – 4 N – 3 N – 2 N – 1 N tC CLKOUT 9002 TD01
Multiplexed Digital Output Bus Timing
tAPA A + 2 A + 4 ANALOG A INPUT A A + 1 A + 3 tAPB B + 2 B + 4 ANALOG B INPUT B B + 1 B + 3 tH tL CLKA = CLKB = MUX DA0-DA13 A – 5 B – 5 A – 4 B – 4 A – 3 B – 3 A – 2 B – 2 A – 1 tD tMD DB0-DB13 B – 5 A – 5 B – 4 A – 4 B – 3 A – 3 B – 2 A – 2 B – 1 tC CLKOUT 9002 TD02 9002f 7
TIMING DIAGRAMS Dual Digital Output Bus Timing
tAP N + 2 N + 4 ANALOG N INPUT N + 1 N + 3 N + 5 tH tL CLKA = CLKB tD D0-D13, OF N – 5 N – 4 N – 3 N – 2 N – 1 N tC CLKOUT 9002 TD01
Multiplexed Digital Output Bus Timing
tAPA A + 2 A + 4 ANALOG A INPUT A A + 1 A + 3 tAPB B + 2 B + 4 ANALOG B INPUT B B + 1 B + 3 tH tL CLKA = CLKB = MUX DA0-DA13 A – 5 B – 5 A – 4 B – 4 A – 3 B – 3 A – 2 B – 2 A – 1 tD tMD DB0-DB13 B – 5 A – 5 B – 4 A – 4 B – 3 A – 3 B – 2 A – 2 B – 1 tC CLKOUT 9002 TD02 9002f 7