Datasheet LTC2483 (Analog Devices) - 9
| Hersteller | Analog Devices |
| Beschreibung | 16-Bit ΔΣ ADC with Easy Drive Input Current Cancellation and I2C Interface |
| Seiten / Seite | 34 / 9 — REF+ (Pin 1), REF– (Pin 3):. SDA (Pin 7):. VCC (Pin 2):. GND (Pin 8):. … |
| Dateiformat / Größe | PDF / 2.9 Mb |
| Dokumentensprache | Englisch |
REF+ (Pin 1), REF– (Pin 3):. SDA (Pin 7):. VCC (Pin 2):. GND (Pin 8):. CA1 (Pin 9):. IN+ (Pin 4), IN– (Pin 5):. CA0/F. 0 (Pin 10):
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LTC2483 pin FuncTions
REF+ (Pin 1), REF– (Pin 3):
Differential Reference Input.
SDA (Pin 7):
Serial Data Output Line of the I2C Interface. The voltage on these pins can have any value between In the transmitter mode (read), the conversion result is GND and VCC as long as the reference positive input, output through the SDA pin. It is an open-drain N-channel REF+, is more positive than the reference negative input, driver and therefore an external pull-up resistor or current REF–, by at least 0.1V. source to VCC is needed.
VCC (Pin 2):
Positive Supply Voltage. Bypass to GND
GND (Pin 8):
Ground. Connect this pin to a ground plane (Pin 8) with a 1µF tantalum capacitor in parallel with 0.1µF through a low impedance connection. ceramic capacitor as close to the part as possible.
CA1 (Pin 9):
Chip Address Control Pin. The CA1 pin
IN+ (Pin 4), IN– (Pin 5):
Differential Analog Input. The volt- is configured as a three state (LOW, HIGH, or floating) age on these pins can have any value between GND – 0.3V address control bit for the device I2C address. and VCC + 0.3V. Within these limits the converter bipolar
CA0/F
input range (V
0 (Pin 10):
Chip Address Control Pin/External Clock IN = IN+ – IN–) extends from –0.5 • VREF to Input Pin. When no transition is detected on the CA0/F 0.5 • V 0 REF. Outside this input range the converter produces pin, it is a two state (HIGH or floating) address control unique overrange and underrange output codes. bit for the device I2C address. When the pin is driven by
SCL (Pin 6):
Serial Clock Pin of the I2C Interface. The an external clock signal with a frequency fEOSC of at least LTC2483 can only act as a slave and the SCL pin only 10kHz, the converter uses this signal as its system clock accepts external serial clock. Data is shifted out the SDA and the fundamental digital filter rejection null is located pin on the falling edges of the SCL clock. at a frequency fEOSC/5120 and sets the chip address CA0 internally to a HIGH. 2483fc Document Outline Features Applications Description Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Converter Characteristics Analog Input and Reference I2C Digital Inputs and Digital Outputs Power Requirements Timing Characteristics I2C Timing Characteristics Typical Performance Characteristics Pin Functions Block Diagram Applications Information Package Description Revision History Typical Application Related Parts
REF+ (Pin 1), REF– (Pin 3):
Differential Reference Input.
SDA (Pin 7):
Serial Data Output Line of the I2C Interface. The voltage on these pins can have any value between In the transmitter mode (read), the conversion result is GND and VCC as long as the reference positive input, output through the SDA pin. It is an open-drain N-channel REF+, is more positive than the reference negative input, driver and therefore an external pull-up resistor or current REF–, by at least 0.1V. source to VCC is needed.
VCC (Pin 2):
Positive Supply Voltage. Bypass to GND
GND (Pin 8):
Ground. Connect this pin to a ground plane (Pin 8) with a 1µF tantalum capacitor in parallel with 0.1µF through a low impedance connection. ceramic capacitor as close to the part as possible.
CA1 (Pin 9):
Chip Address Control Pin. The CA1 pin
IN+ (Pin 4), IN– (Pin 5):
Differential Analog Input. The volt- is configured as a three state (LOW, HIGH, or floating) age on these pins can have any value between GND – 0.3V address control bit for the device I2C address. and VCC + 0.3V. Within these limits the converter bipolar
CA0/F
input range (V
0 (Pin 10):
Chip Address Control Pin/External Clock IN = IN+ – IN–) extends from –0.5 • VREF to Input Pin. When no transition is detected on the CA0/F 0.5 • V 0 REF. Outside this input range the converter produces pin, it is a two state (HIGH or floating) address control unique overrange and underrange output codes. bit for the device I2C address. When the pin is driven by
SCL (Pin 6):
Serial Clock Pin of the I2C Interface. The an external clock signal with a frequency fEOSC of at least LTC2483 can only act as a slave and the SCL pin only 10kHz, the converter uses this signal as its system clock accepts external serial clock. Data is shifted out the SDA and the fundamental digital filter rejection null is located pin on the falling edges of the SCL clock. at a frequency fEOSC/5120 and sets the chip address CA0 internally to a HIGH. 2483fc Document Outline Features Applications Description Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Converter Characteristics Analog Input and Reference I2C Digital Inputs and Digital Outputs Power Requirements Timing Characteristics I2C Timing Characteristics Typical Performance Characteristics Pin Functions Block Diagram Applications Information Package Description Revision History Typical Application Related Parts