Datasheet LTC2460, LTC2462 (Analog Devices) - 10

LTC2460/LTC2462
applicaTions inForMaTion Table 1. LTC2460/LTC2462 Output Data Format SINGLE ENDED INPUT VIN DIFFERENTIAL INPUT VOLTAGE D15 D14 D13 D12...D2 D1 D0 CORRESPONDING (LTC2460) V + – IN – VIN (LTC2462) (MSB) (LSB) DECIMAL VALUE
≥VREF ≥VREF 1 1 1 1 1 1 65535 VREF – 1LSB VREF – 1LSB 1 1 1 1 1 0 65534 0.75 • VREF 0.5 • VREF 1 1 0 0 0 0 49152 0.75 • VREF – 1LSB 0.5 • VREF – 1LSB 1 0 1 1 1 1 49151 0.5 • VREF 0 1 0 0 0 0 0 32768 0.5 • VREF – 1LSB –1LSB 0 1 1 1 1 1 32767 0.25 • VREF –0.5 • VREF 0 1 0 0 0 0 16384 0.25 • VREF – 1LSB –0.5 • VREF – 1LSB 0 0 1 1 1 1 16383 0 ≤ –VREF 0 0 0 0 0 0 0 The LTC2460 (single-ended input) output code is a direct the next conversion is complete. It will remain powered binary encoded result, see Table 1. down until CS is pulled low. The reference startup time During the data output operation the CS input pin must is approximately 12ms. In order to ensure a stable refer- be pulled low (CS = LOW). The data output process starts ence for the following conversions, either the data input/ with the most significant bit of the result being present at output time should be delayed 12ms after CS goes low or the SDO output pin (SDO = D15) once CS goes low. A new the first conversion following a reference start up should data bit appears at the SDO output pin after each falling be discarded. If SDI is tied HIGH (LTC2460 operating in edge detected at the SCK input pin. The output data can 30Hz mode) the SLP mode is disabled. be reliably latched on the rising edge of SCK.
Conversion Status Monitor Data Input Format
For certain applications, the user may wish to monitor the The data input word is 4 bits long and consists of two en- LTC2460/LTC2462 conversion status. This can be achieved able bits (EN1 and EN2) and two programming bits (SPD by holding SCK HIGH during the conversion cycle. In and SLP). EN1 is applied to the first rising edge of SCK this condition, whenever the CS input pin is pulled low after the conversion is complete. Programming is enabled (CS = LOW), the SDO output pin will provide an indication by setting EN1 = 1 and EN2 = 0. of the conversion status. SDO = HIGH is an indication of a conversion cycle in progress while SDO = LOW is an The speed bit (SPD) is only used by the LTC2460. In the indication of a completed conversion cycle. An example default mode, SPD = 0, the output rate is 60Hz and con- of such a sequence is shown in Figure 5. tinuous background offset calibration is not performed. By changing the SPD bit to 1, background offset calibration is Conversion status monitoring, while possible, is not re- performed and the output rate is reduced to 30Hz. Alterna- quired for the LTC2460/LTC2462 as its conversion time is tively, SDI can be tied directly to ground (SPD = 0) or V fixed and typically 16.6ms (23ms maximum). Therefore, CC (SPD = 1), eliminating the need to program the device. The external timing can be used to determine the completion of a LTC2462 data output rate is always 60Hz and background conversion cycle. offset calibration is performed (SPD = don’t care).
SERIAL INTERFACE
The sleep bit (SLP) is used to power down the on chip reference. In the default mode, the reference remains The LTC2460/LTC2462 transmit the conversion result and powered up even when the ADC is powered down. If the receive the start of conversion command through a syn- SLP bit is set HIGH, the reference will power down after chronous 2-, 3- or 4-wire interface. This interface can be 24602fa 10 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Electrical Characteristics Analog Inputs Power Requirements Digital Inputs and Digital Outputs Timing Characteristics Typical Performance Characteristics Pin Functions Applications Information Package Description Revision History Typical Application Related Parts