Datasheet LTC2453 (Analog Devices) - 9

LTC2453
APPLICATIONS INFORMATION
SDA t t SU(DAT) tf t r tr LOW tf tHD(SDA) tSP tBUF SCL tHD(STA) tSU(STA) tSU(STO) S tHD(DAT) tHIGH Sr P S 2453 F03
Figure 3. Definition of Timing for Fast/Standard Mode Devices on the I2C Bus
START timing is functionally identical to the START and
OPERATION SEQUENCE
is used for reading from the device before the initiation of a new conversion.
Continuous Read
Conversions from the LTC2453 can be continuously
Data Transferring
read, see Figure 6. At the end of a read operation, a new After the START condition, the I2C bus is busy and data conversion automatically begins. At the conclusion of transfer can begin between the master and the addressed the conversion cycle, the next result may be read using slave. Data is transferred over the bus in groups of nine the method described above. If the conversion cycle is bits, one byte followed by one acknowledge (ACK) bit. The not complete and a valid address selects the device, the master releases the SDA line during the ninth SCL clock LTC2453 generates a NAK signal indicating the conversion cycle. The slave device can issue an ACK by pulling SDA cycle is in progress. LOW or issue a Not Acknowledge (NAK) by leaving the SDA line HIGH impedance (the external pull-up resistor
Discarding a Conversion Result and Initiating a New
will hold the line HIGH). Change of data only occurs while
Conversion
the clock line (SCL) is LOW. It is possible to start a new conversion without reading
Data Format
the old result, as shown in Figure 7. Following a valid 7-bit address, a read request (R) bit, and a valid ACK, a STOP After a START condition, the master sends a 7-bit address command will start a new conversion. followed by a read request (R) bit. The bit R is 1 for a Read Request. If the 7-bit address matches the LTC2453’s address (hard-wired at 0010100) the ADC is selected.
PRESERVING THE CONVERTER ACCURACY
When the device is addressed during the conversion The LTC2453 is designed to dramatically reduce the conver- state, it does not accept the request and issues a NAK by sion result’s sensitivity to device decoupling, PCB layout, leaving the SDA line HIGH. If the conversion is complete, antialiasing circuits, line and frequency perturbations. the LTC2453 issues an ACK by pulling the SDA line LOW. Nevertheless, in order to preserve the high accuracy capa- Following the ACK, the LTC2453 can output data. The data bility of this part, some simple precautions are desirable. output stream is 16 bits long and is shifted out on the
Digital Signal Levels
falling edges of SCL (see Figure 4). The first bit output by the LTC2453, the MSB, is the sign, which is 1 for V + IN ≥ Due to the nature of CMOS logic, it is advisable to keep V – + – IN and 0 for VIN < VIN (see Table 1). The MSB (D15) is input digital signals near GND or VCC. Voltages in the followed by successively less significant bits (D14, D13…) range of 0.5V to VCC – 0.5V may result in additional cur- until the LSB is output by the LTC2453. This sequence is rent leakage from the part. shown in Figure 5. 2453fc 9 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Analog Inputs And References Power Requirements I2C Inputs And Outputs I2C Timing Characteristics Typical Performance Characteristics Pin Functions Block Diagram Applications Information Typical Application Package Description Revision History Related Parts