Datasheet LTC2450-1 (Analog Devices) - 10
| Hersteller | Analog Devices |
| Beschreibung | Easy-to-Use, Ultra-Tiny 16-Bit ΔΣ ADC |
| Seiten / Seite | 20 / 10 — APPLICATIONS INFORMATION. Serial Clock Idle-High (CPOL = 1) Examples. … |
| Dateiformat / Größe | PDF / 208 Kb |
| Dokumentensprache | Englisch |
APPLICATIONS INFORMATION. Serial Clock Idle-High (CPOL = 1) Examples. Serial Clock Idle-Low (CPOL = 0) Examples
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LTC2450-1
APPLICATIONS INFORMATION Serial Clock Idle-High (CPOL = 1) Examples
the falling edge of the serial clock (SCK). A 17th clock pulse is used to trigger a new conversion cycle. In Figure 5, following a conversion cycle the LTC2450-1 automatically enters the low power sleep mode. The user
Serial Clock Idle-Low (CPOL = 0) Examples
can monitor the conversion status at convenient intervals using CS and SDO. In Figure 7, following a conversion cycle the LTC2450-1 CS automatically enters the low power sleep state. The user is pulled LOW while SCK is HIGH to test whether or not determines data availability (and the end of conversion) the chip is in the CONVERT state. While in the CONVERT based upon external timing. The user then pulls CS low state, SDO is HIGH while CS is LOW. In the SLEEP state, (CS = ↓) and uses 16 clock cycles to transfer the result. SDO is LOW while CS is LOW. These tests are not required Following the 16th rising edge of the clock, CS is pulled high operational steps but may be useful for some applications. (CS = ↑), which triggers a new conversion. When the data is available, the user applies 16 clock cycles The timing diagram in Figure 8 is identical to that of Figure 7, to transfer the result. The CS rising edge is then used to except in this case a new conversion is triggered by SCK. initiate a new conversion. The 16th SCK falling edge triggers a new conversion cycle The operation example of Figure 6 is identical to that of and the CS signal is subsequently pulled high. Figure 5, except the new conversion cycle is triggered by CS SD0 D15 D14 D13 D12 D2 D1 D0 SCK clk1 clk2 clk3 clk4 clk15 clk16 CONVERT SLEEP DATA OUTPUT CONVERT LOW I 24501 F05 CC
Figure 5. Idle-High (CPOL = 1) Serial Clock Operation Example. The Rising Edge of CS Starts a New Conversion
CS SD0 D15 D14 D13 D12 D2 D1 D0 SCK clk1 clk2 clk3 clk4 clk15 clk16 clk17 CONVERT SLEEP DATA OUTPUT CONVERT LOW I 24501 F06 CC
Figure 6. Idle-High (CPOL = 1) Clock Operation Example. A 17th Clock Pulse is Used to Trigger a New Conversion Cycle
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APPLICATIONS INFORMATION Serial Clock Idle-High (CPOL = 1) Examples
the falling edge of the serial clock (SCK). A 17th clock pulse is used to trigger a new conversion cycle. In Figure 5, following a conversion cycle the LTC2450-1 automatically enters the low power sleep mode. The user
Serial Clock Idle-Low (CPOL = 0) Examples
can monitor the conversion status at convenient intervals using CS and SDO. In Figure 7, following a conversion cycle the LTC2450-1 CS automatically enters the low power sleep state. The user is pulled LOW while SCK is HIGH to test whether or not determines data availability (and the end of conversion) the chip is in the CONVERT state. While in the CONVERT based upon external timing. The user then pulls CS low state, SDO is HIGH while CS is LOW. In the SLEEP state, (CS = ↓) and uses 16 clock cycles to transfer the result. SDO is LOW while CS is LOW. These tests are not required Following the 16th rising edge of the clock, CS is pulled high operational steps but may be useful for some applications. (CS = ↑), which triggers a new conversion. When the data is available, the user applies 16 clock cycles The timing diagram in Figure 8 is identical to that of Figure 7, to transfer the result. The CS rising edge is then used to except in this case a new conversion is triggered by SCK. initiate a new conversion. The 16th SCK falling edge triggers a new conversion cycle The operation example of Figure 6 is identical to that of and the CS signal is subsequently pulled high. Figure 5, except the new conversion cycle is triggered by CS SD0 D15 D14 D13 D12 D2 D1 D0 SCK clk1 clk2 clk3 clk4 clk15 clk16 CONVERT SLEEP DATA OUTPUT CONVERT LOW I 24501 F05 CC
Figure 5. Idle-High (CPOL = 1) Serial Clock Operation Example. The Rising Edge of CS Starts a New Conversion
CS SD0 D15 D14 D13 D12 D2 D1 D0 SCK clk1 clk2 clk3 clk4 clk15 clk16 clk17 CONVERT SLEEP DATA OUTPUT CONVERT LOW I 24501 F06 CC
Figure 6. Idle-High (CPOL = 1) Clock Operation Example. A 17th Clock Pulse is Used to Trigger a New Conversion Cycle
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