Datasheet LTC2446, LTC2447 (Analog Devices) - 10
| Hersteller | Analog Devices |
| Beschreibung | 24-Bit High Speed 8-Channel ∆Σ ADCs with Selectable Multiple Reference Inputs |
| Seiten / Seite | 30 / 10 — APPLICATIONS INFORMATION. Figure 3. SDI Speed/Resolution, Channel … |
| Dateiformat / Größe | PDF / 619 Kb |
| Dokumentensprache | Englisch |
APPLICATIONS INFORMATION. Figure 3. SDI Speed/Resolution, Channel Selection, and Data Output Timing. SERIAL INTERFACE PINS
Modelllinie für dieses Datenblatt
Textversion des Dokuments
LTC2446/LTC2447
APPLICATIONS INFORMATION
CS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 32 SCK SDI 1 0 EN SGL ODD GLBL A1 A0 OSR3 OSR2 OSR1 OSR0 TWOX BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21 BIT 20 BIT 19 BIT 0 Hi-Z Hi-Z SDO EOC “0” SIG MSB LSB BUSY 24467 F03
Figure 3. SDI Speed/Resolution, Channel Selection, and Data Output Timing
shifted out on the falling edge of the 31st SCK and may corresponding to the +FS + 1LSB. For differential input be latched on the rising edge of the 32nd SCK pulse. On voltages below –FS, the conversion result is clamped to the falling edge of the 32nd SCK pulse, SDO goes HIGH the value corresponding to –FS – 1LSB. indicating the initiation of a new conversion cycle. This bit serves as EOC (Bit 31) for the next conversion cycle.
SERIAL INTERFACE PINS
Table 2 summarizes the output data format. The LTC2446/LTC2447 transmit the conversion results As long as the voltage on the IN+ and IN– pins is main- and receive the start of conversion command through a tained within the –0.3V to (VCC + 0.3V) absolute maximum synchronous 3- or 4-wire interface. During the conver- operating range, a conversion result is generated for any sion and sleep states, this interface can be used to assess differential input voltage VIN from –FS = –0.5 • VREF to the converter status and during the data output state it is +FS = 0.5 • VREF. For differential input voltages greater used to read the conversion result and program the speed, than +FS, the conversion result is clamped to the value resolution and input channel.
Table 2. LTC2446/LTC2447 Output Data Format Differential Input Voltage Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 … Bit 0 VIN* EOC DMY SIG MSB
VIN* ≥ 0.5 • VREF** 0 0 1 1 0 0 0 … 0 0.5 • VREF** – 1LSB 0 0 1 0 1 1 1 … 1 0.25 • VREF** 0 0 1 0 1 0 0 … 0 0.25 • VREF** – 1LSB 0 0 1 0 0 1 1 … 1 0 0 0 1 0 0 0 0 … 0 –1LSB 0 0 0 1 1 1 1 … 1 –0.25 • VREF** 0 0 0 1 1 0 0 … 0 –0.25 • VREF** – 1LSB 0 0 0 1 0 1 1 … 1 –0.5 • VREF** 0 0 0 1 0 0 0 … 0 VIN* < –0.5 • VREF** 0 0 0 0 1 1 1 … 1 *The differential input voltage VIN = IN+ – IN–. **The differential reference voltage VREF = REF+ – REF–. 24467fb 10 For more information www.linear.com/LTC2446 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Test Circuit Timing Diagram Operation Applications Information Package Description Revision History Typical Application Related Parts
APPLICATIONS INFORMATION
CS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 32 SCK SDI 1 0 EN SGL ODD GLBL A1 A0 OSR3 OSR2 OSR1 OSR0 TWOX BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21 BIT 20 BIT 19 BIT 0 Hi-Z Hi-Z SDO EOC “0” SIG MSB LSB BUSY 24467 F03
Figure 3. SDI Speed/Resolution, Channel Selection, and Data Output Timing
shifted out on the falling edge of the 31st SCK and may corresponding to the +FS + 1LSB. For differential input be latched on the rising edge of the 32nd SCK pulse. On voltages below –FS, the conversion result is clamped to the falling edge of the 32nd SCK pulse, SDO goes HIGH the value corresponding to –FS – 1LSB. indicating the initiation of a new conversion cycle. This bit serves as EOC (Bit 31) for the next conversion cycle.
SERIAL INTERFACE PINS
Table 2 summarizes the output data format. The LTC2446/LTC2447 transmit the conversion results As long as the voltage on the IN+ and IN– pins is main- and receive the start of conversion command through a tained within the –0.3V to (VCC + 0.3V) absolute maximum synchronous 3- or 4-wire interface. During the conver- operating range, a conversion result is generated for any sion and sleep states, this interface can be used to assess differential input voltage VIN from –FS = –0.5 • VREF to the converter status and during the data output state it is +FS = 0.5 • VREF. For differential input voltages greater used to read the conversion result and program the speed, than +FS, the conversion result is clamped to the value resolution and input channel.
Table 2. LTC2446/LTC2447 Output Data Format Differential Input Voltage Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 … Bit 0 VIN* EOC DMY SIG MSB
VIN* ≥ 0.5 • VREF** 0 0 1 1 0 0 0 … 0 0.5 • VREF** – 1LSB 0 0 1 0 1 1 1 … 1 0.25 • VREF** 0 0 1 0 1 0 0 … 0 0.25 • VREF** – 1LSB 0 0 1 0 0 1 1 … 1 0 0 0 1 0 0 0 0 … 0 –1LSB 0 0 0 1 1 1 1 … 1 –0.25 • VREF** 0 0 0 1 1 0 0 … 0 –0.25 • VREF** – 1LSB 0 0 0 1 0 1 1 … 1 –0.5 • VREF** 0 0 0 1 0 0 0 … 0 VIN* < –0.5 • VREF** 0 0 0 0 1 1 1 … 1 *The differential input voltage VIN = IN+ – IN–. **The differential reference voltage VREF = REF+ – REF–. 24467fb 10 For more information www.linear.com/LTC2446 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Test Circuit Timing Diagram Operation Applications Information Package Description Revision History Typical Application Related Parts