Datasheet LTC2442 (Analog Devices) - 7

LTC2442
PIN FUNCTIONS SCK (Pin 1):
Bidirectional Digital Clock Pin. In internal serial
–INA (Pin 13):
Amplifier A negative Input. By shorting this clock operation mode, SCK is used as a digital output for pin to OUTA (Pin 12) the amplifier becomes a buffer with the internal serial interface clock during the data output unity gain. Alternatively, an external resistor network may period. In the external serial clock operation mode, SCK be added here for gains greater than 1. is used as the digital input for the external serial interface
NC (Pins 14, 15, 16, 20, 22, 23):
No Connect. These pins clock during the data output period. The serial clock op- should be left floating or tied to Ground. eration mode is determined by the logic level applied to EXT (Pin 3).
OUTB (Pin 17):
Amplifier B Output. Must be compensated with 0.1µF or greater capacitor. Drives the ADCINB ADC
BUSY (Pin 2):
Conversion in Progress Indicator. This pin input (Pin 10). is HIGH while the conversion is in progress and goes LOW indicating the conversion is complete and data is ready.
–INB (Pin 18):
Amplifier B negative Input. By shorting this It remains LOW during the sleep and data output states. pin to OUTB (Pin 17) the amplifier becomes a buffer with At the conclusion of the data output state, it goes HIGH unity gain. Alternatively, an external resistor network may indicating a new conversion has begun. be added here for gains greater than 1.
EXT (Pin 3):
Internal/External SCK Selection Pin. This pin
+INB (Pin 19):
Amplifier B positive Input. Must tie to the is used to select internal or external SCK for outputting/ Multiplexer output MUXOUTB (Pin 26). inputting data. If EXT is tied low, the device is in the
V+ (Pin 21):
Amplifier positive supply voltage input. May external SCK mode and data is shifted out of the device tie to VCC or an external supply voltage up to 15V. Bypass under the control of a user applied serial clock. If EXT is to GND with 1µF capacitor. tied high, the internal serial clock mode is selected. The device generates its own SCK signal and outputs this on
V– (Pin 24):
Amplifier Negative supply voltage input. May the SCK pin. A framing signal BUSY (Pin 2) goes low tie to GND or an external supply voltage as low as –15V. indicating data is being output. Bypass to GND with a 1µF capacitor.
GND (Pins 4, 5, 32):
Ground. Multiple ground pins inter-
+INA (Pin 25):
Amplifier A positive Input. Must tie to the nally connected for optimum ground current flow and V Multiplexer output MUXOUTA (Pin 27). CC decoupling. Connect each one of these pins to a common
MUXOUTB (Pin 26):
Multiplexer Output. Must tie to +INB ground plane through a low impedance connection. Al three amplifier input (Pin 19). pins must be connected to ground for proper operation.
MUXOUTA (Pin 27):
Multiplexer Output. Must tie to +INA
CH0 to CH3 (Pins 6, 7, 8, 9):
Analog Inputs. May be amplifier input (Pin 25). programmed for single-ended or differential mode. (See
COM (Pin 28):
The common negative input (SEL–) for all Table 3) single ended multiplexer configurations. The voltage on
ADCINB (Pin 10):
ADC Input. Must tie to the amplifier CH0-CH3 and COM pins can have any value between GND output, OUTB (Pin 17). –0.3V to VCC +0.3V. Within these limits, the two selected
ADCINA (Pin 11):
ADC Input. Must tie to the amplifier inputs (SEL+ and SEL–) provide a bipolar input range (VIN output, OUTA (Pin 12). = SEL+ – SEL–) from –0.5 • VREF to 0.5 • VREF . Outside this input range, the converter produces unique over-range
OUTA (Pin 12):
Amplifier A output. Must be compensated and under-range output codes. with 0.1µF or greater capacitor. Drives the ADCINA ADC input (Pin 11). 2442fb For more information www.linear.com/LTC2442 7