Datasheet LTC2420 (Analog Devices) - 10
| Hersteller | Analog Devices |
| Beschreibung | 20-Bit µPower No Latency ∆Σ™ ADC in SO-8 |
| Seiten / Seite | 36 / 10 — APPLICATIO S I FOR ATIO. Converter Operation Cycle. Figure 2. LTC2420 … |
| Dateiformat / Größe | PDF / 405 Kb |
| Dokumentensprache | Englisch |
APPLICATIO S I FOR ATIO. Converter Operation Cycle. Figure 2. LTC2420 State Transition Diagram
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LTC2420
U U W U APPLICATIO S I FOR ATIO
The LTC2420 is pin compatible with the LTC2400. The two Once CS is pulled LOW, the device begins outputting the devices are designed to allow the user to incorporate conversion result. There is no latency in the conversion either device in the same design with no modifications. result. The data output corresponds to the conversion just While the LTC2420 output word length is 24 bits (as performed. This result is shifted out on the serial data out opposed to the 32-bit output of the LTC2400), its output pin (SDO) under the control of the serial clock (SCK). Data clock timing can be identical to the LTC2400. As shown in is updated on the falling edge of SCK allowing the user to Figure 1, the LTC2420 data output is concluded on the reliably latch data on the rising edge of SCK, see Figure 4. falling edge of the 24th serial clock (SCK). In order to The data output state is concluded once 24 bits are read maintain drop-in compatibility with the LTC2400, it is out of the ADC or when CS is brought HIGH. The device possible to clock the LTC2420 with an additional 8 serial automatically initiates a new conversion cycle and the clock pulses. This results in 8 additional output bits which cycle repeats. are always logic HIGH. Through timing control of the CS and SCK pins, the LTC2420 offers several flexible modes of operation
Converter Operation Cycle
(internal or external SCK and free-running conversion The LTC2420 is a low power, delta-sigma analog-to- modes). These various modes do not require digital converter with an easy to use 3-wire serial interface. programming configuration registers; moreover, they do Its operation is simple and made up of three states. The converter operating cycle begins with the conversion, CONVERT followed by a low power sleep state and concluded with the data output (see Figure 2). The 3-wire interface con- SLEEP sists of serial data output (SDO), a serial clock (SCK) and a chip select (CS). Initially, the LTC2420 performs a conversion. Once the 1 CS AND conversion is complete, the device enters the sleep state. SCK While in this sleep state, power consumption is reduced by 0 an order of magnitude. The part remains in the sleep state as long as CS is logic HIGH. The conversion result is held DATA OUTPUT indefinitely in a static shift register while the converter is 2420 F02 in the sleep state.
Figure 2. LTC2420 State Transition Diagram
CS 8 8 8 8 (OPTIONAL) SCK SDO EOC = 1 EOC = 0 DATA OUT EOC = 1 4 STATUS BITS 20 DATA BITS LAST 8 BITS ALWAYS 1 CONVERSION SLEEP DATA OUTPUT CONVERSION 2420 F01
Figure 1. LTC2420 Compatible Timing with the LTC2400
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U U W U APPLICATIO S I FOR ATIO
The LTC2420 is pin compatible with the LTC2400. The two Once CS is pulled LOW, the device begins outputting the devices are designed to allow the user to incorporate conversion result. There is no latency in the conversion either device in the same design with no modifications. result. The data output corresponds to the conversion just While the LTC2420 output word length is 24 bits (as performed. This result is shifted out on the serial data out opposed to the 32-bit output of the LTC2400), its output pin (SDO) under the control of the serial clock (SCK). Data clock timing can be identical to the LTC2400. As shown in is updated on the falling edge of SCK allowing the user to Figure 1, the LTC2420 data output is concluded on the reliably latch data on the rising edge of SCK, see Figure 4. falling edge of the 24th serial clock (SCK). In order to The data output state is concluded once 24 bits are read maintain drop-in compatibility with the LTC2400, it is out of the ADC or when CS is brought HIGH. The device possible to clock the LTC2420 with an additional 8 serial automatically initiates a new conversion cycle and the clock pulses. This results in 8 additional output bits which cycle repeats. are always logic HIGH. Through timing control of the CS and SCK pins, the LTC2420 offers several flexible modes of operation
Converter Operation Cycle
(internal or external SCK and free-running conversion The LTC2420 is a low power, delta-sigma analog-to- modes). These various modes do not require digital converter with an easy to use 3-wire serial interface. programming configuration registers; moreover, they do Its operation is simple and made up of three states. The converter operating cycle begins with the conversion, CONVERT followed by a low power sleep state and concluded with the data output (see Figure 2). The 3-wire interface con- SLEEP sists of serial data output (SDO), a serial clock (SCK) and a chip select (CS). Initially, the LTC2420 performs a conversion. Once the 1 CS AND conversion is complete, the device enters the sleep state. SCK While in this sleep state, power consumption is reduced by 0 an order of magnitude. The part remains in the sleep state as long as CS is logic HIGH. The conversion result is held DATA OUTPUT indefinitely in a static shift register while the converter is 2420 F02 in the sleep state.
Figure 2. LTC2420 State Transition Diagram
CS 8 8 8 8 (OPTIONAL) SCK SDO EOC = 1 EOC = 0 DATA OUT EOC = 1 4 STATUS BITS 20 DATA BITS LAST 8 BITS ALWAYS 1 CONVERSION SLEEP DATA OUTPUT CONVERSION 2420 F01
Figure 1. LTC2420 Compatible Timing with the LTC2400
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