Datasheet LTC2385-18 (Analog Devices) - 9

LTC2385-18
PIN FUNCTIONS GND (Pins 1, 4, 10, 21, 26, 29 ):
Ground. Connect to a
PD (Pin 13):
Digital input that enables power-down mode. solid ground plane in the PCB underneath the ADC. When PD is low, the LTC2385 enters power-down mode,
IN+, IN– (Pins 2, 3):
Positive and Negative Differential and all circuitry (including the LVDS interface) is shut Analog Inputs. The inputs must be driven differentially down. When PD is high, the part operates normally. Logic and 180° out of phase, with a common mode voltage of levels are determined by OVDD. 2.048V. The differential input range is ±4.096V (each input
TESTPAT (Pin 14):
Digital input that forces the LVDS data pin swings from 0V to 4.096V.) outputs to be a test pattern. When TESTPAT is high, the
REFGND (Pins 5, 6):
Reference Ground. The two pins digital outputs are a test pattern. When TESTPAT is low, should be shorted together and connected to the refer- the digital outputs are the ADC conversion result. Logic ence bypass capacitor with a short, wide trace. In ad- levels are determined by OVDD. dition, connect the pins to the exposed pad (Pin 33). A
DB–/DB+, DA–/DA+ (Pins 15/16, 17/18):
Serial LVDS suggested layout is shown in the ADC Reference section Data Outputs. In one-lane output mode, DB–/DB+ are not of the data sheet. used and their LVDS driver is disabled to reduce power
REFBUF (Pins 7, 8):
Internal Reference Buffer Output. consumption. The output voltage of the internal 2× gain reference buffer,
DCO–/DCO+ (Pins 19/20):
LVDS Data Clock Output. This nominally 4.096V, is provided on this pin. The two pins is an echoed version of CLK–/CLK+ that can be used to should be shorted together and bypassed to REFGND with latch the data outputs. a 10µF (X7R, 0805 size) ceramic capacitor. If the internal
OV
buffer is not required, tie REFIN to GND to power down
DD (Pin 22):
2.5V Output Power Supply. The range of OV the buffer and connect an external 4.096V reference to DD is 2.375V to 2.625V. Bypass to GND with a 0.1μF ceramic capacitor. REFBUF.
CLK–/CLK+ (Pins 23/24):
LVDS Clock Input. This is an
REFIN (Pin 9):
Internal Reference Output/Reference Buffer externally applied clock that serially shifts out the conver- Input. The output voltage of the internal reference, nomi- sion result. nally 2.048V, is output on this pin. An external reference can be applied to REFIN if a more accurate reference is
TWOLANES (Pin 25):
Digital input that enables two-lane required. For increased filtering of reference noise, bypass output mode. When TWOLANES is high (two-lane output this pin to GND using a 0.1µF or larger ceramic capacitor. mode), the ADC outputs two bits at a time on DA–/DA+ If the internal reference buffer is not used, tie REFIN to and DB–/DB+. When TWOLANES is low (one-lane output GND to power down the buffer and connect an external mode), the ADC outputs one bit at a time on DA–/DA+, and buffered reference to REFBUF. DB–/DB+ are disabled. Logic levels are determined by VDDL.
VDD (Pins 11, 12):
5V Analog Power Supply. The range
CNV–/CNV+ (Pins 27/28):
Conversion Start LVDS Input. of VDD is 4.75V to 5.25V. The two pins should be shorted A rising edge on CNV+ puts the internal sample-and-hold together and bypassed to GND with 0.1μF and 10μF ce- into the hold mode and starts a conversion cycle. CNV+ ramic capacitors. can also be driven with a 2.5V CMOS signal if CNV– is tied to GND. 238518f For more information www.linear.com/LTC2385-18 9 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Electrical Characteristics Pin Configuration Converter Characteristics Dynamic Accuracy Internal Reference Characteristics Reference Buffer Characteristics Digital Inputs and Digital Outputs Power Requirements ADC Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagram Applications Information Package Description Typical Application Related Parts