Datasheet LTC2381-16 (Analog Devices) - 9
| Hersteller | Analog Devices |
| Beschreibung | 16-Bit, 250ksps, Low Power SAR ADC with Serial Interface |
| Seiten / Seite | 26 / 9 — TIMING DIAGRAM. Conversion Timing Using the Serial Interface. … |
| Dateiformat / Größe | PDF / 2.1 Mb |
| Dokumentensprache | Englisch |
TIMING DIAGRAM. Conversion Timing Using the Serial Interface. APPLICATIONS INFORMATION OVERVIEW. CONVERTER OPERATION
Modelllinie für dieses Datenblatt
- LTC2381CDE-16#PBF LTC2381CDE-16#PBF LTC2381CDE-16#TRPBF LTC2381CDE-16#TRPBF LTC2381CMS-16#PBF LTC2381CMS-16#PBF LTC2381CMS-16#TRPBF LTC2381CMS-16#TRPBF LTC2381HMS-16#PBF LTC2381HMS-16#PBF LTC2381HMS-16#TRPBF LTC2381HMS-16#TRPBF LTC2381IDE-16#PBF LTC2381IDE-16#PBF LTC2381IDE-16#TRPBF LTC2381IDE-16#TRPBF LTC2381IMS-16#PBF LTC2381IMS-16#PBF LTC2381IMS-16#TRPBF LTC2381IMS-16#TRPBF
Textversion des Dokuments
LTC2381-16
TIMING DIAGRAM Conversion Timing Using the Serial Interface
CHAIN, RDL/SDI = 0 POWER-UP CNV POWER-DOWN CONVERT BUSY HOLD ACQUIRE SCK D15 D14 D13 D2 D1 D0 SDO 238116 TD01
APPLICATIONS INFORMATION OVERVIEW CONVERTER OPERATION
The LTC2381-16 is a low noise, low power, high speed 16-bit A rising edge on the CNV pin initiates a conversion. During successive approximation register (SAR) ADC. Operating the conversion phase, the 16-bit CDAC is sequenced from a single 2.5V supply, the LTC2381-16 supports a through a successive approximation algorithm, effec- large ±2.5V fully differential input range, making it ideal tively comparing the sampled input with binary-weighted for high performance applications which require a wide fractions of the reference voltage (e.g. VREF/2, VREF/4 … dynamic range. The LTC2381-16 achieves ±2LSB INL max, VREF/65536) using the differential comparator. At the end no missing codes at 16-bits and 92dB SNR. of conversion, the CDAC output approximates the sampled Fast 250ksps throughput with no cycle latency makes the analog input. The ADC control logic then prepares the 16- LTC2381-16 ideally suited for a wide variety of high speed bit digital output code for serial transfer. applications. An internal oscillator sets the conversion time, easing external timing considerations. The LTC2381-16
TRANSFER FUNCTION
dissipates only 3.25mW at 250ksps, while an auto The LTC2381-16 digitizes the full-scale voltage of 2 × REF power-down feature is provided to further reduce power into 216 levels, resulting in an LSB size of 76µV with dissipation during inactive periods. REF = 2.5V. The ideal transfer function is shown in Figure 2. The LTC2381-16 features a proprietary sampling archi- The output data is in 2’s complement format. tecture that enables the ADC to begin acquiring the next sample during the current conversion. The resulting
ANALOG INPUT
extended acquisition time of 3.25µs allows the use of extremely low power ADC drivers. The analog inputs of the LTC2381-16 are fully differential in order to maximize the signal swing that can be digitized. The analog inputs can be modeled by the equivalent circuit 238116fa For more information www.linear.com/LTC2381-16 9
TIMING DIAGRAM Conversion Timing Using the Serial Interface
CHAIN, RDL/SDI = 0 POWER-UP CNV POWER-DOWN CONVERT BUSY HOLD ACQUIRE SCK D15 D14 D13 D2 D1 D0 SDO 238116 TD01
APPLICATIONS INFORMATION OVERVIEW CONVERTER OPERATION
The LTC2381-16 is a low noise, low power, high speed 16-bit A rising edge on the CNV pin initiates a conversion. During successive approximation register (SAR) ADC. Operating the conversion phase, the 16-bit CDAC is sequenced from a single 2.5V supply, the LTC2381-16 supports a through a successive approximation algorithm, effec- large ±2.5V fully differential input range, making it ideal tively comparing the sampled input with binary-weighted for high performance applications which require a wide fractions of the reference voltage (e.g. VREF/2, VREF/4 … dynamic range. The LTC2381-16 achieves ±2LSB INL max, VREF/65536) using the differential comparator. At the end no missing codes at 16-bits and 92dB SNR. of conversion, the CDAC output approximates the sampled Fast 250ksps throughput with no cycle latency makes the analog input. The ADC control logic then prepares the 16- LTC2381-16 ideally suited for a wide variety of high speed bit digital output code for serial transfer. applications. An internal oscillator sets the conversion time, easing external timing considerations. The LTC2381-16
TRANSFER FUNCTION
dissipates only 3.25mW at 250ksps, while an auto The LTC2381-16 digitizes the full-scale voltage of 2 × REF power-down feature is provided to further reduce power into 216 levels, resulting in an LSB size of 76µV with dissipation during inactive periods. REF = 2.5V. The ideal transfer function is shown in Figure 2. The LTC2381-16 features a proprietary sampling archi- The output data is in 2’s complement format. tecture that enables the ADC to begin acquiring the next sample during the current conversion. The resulting
ANALOG INPUT
extended acquisition time of 3.25µs allows the use of extremely low power ADC drivers. The analog inputs of the LTC2381-16 are fully differential in order to maximize the signal swing that can be digitized. The analog inputs can be modeled by the equivalent circuit 238116fa For more information www.linear.com/LTC2381-16 9