Datasheet LTC2377-18 (Analog Devices) - 10

LTC2377-18
APPLICATIONS INFORMATION OVERVIEW TRANSFER FUNCTION
The LTC2377-18 is a low noise, low power, high speed 18-bit The LTC2377-18 digitizes the full-scale voltage of 2 × REF successive approximation register (SAR) ADC. Operating into 218 levels, resulting in an LSB size of 38µV with from a single 2.5V supply, the LTC2377-18 supports a REF = 5V. The ideal transfer function is shown in Figure 2. large and flexible ±VREF fully differential input range with The output data is in 2’s complement format. VREF ranging from 2.5V to 5.1V, making it ideal for high performance applications which require a wide dynamic 011...111 range. The LTC2377-18 achieves ±1.75LSB INL max, no 011...110 BIPOLAR missing codes at 18 bits and 102dB SNR. ZERO Fast 500ksps throughput with no cycle latency makes 000...001 000...000 the LTC2377-18 ideally suited for a wide variety of high 111...111 speed applications. An internal oscillator sets the con- 111...110 version time, easing external timing considerations. The LTC2377-18 dissipates only 6.8mW at 500ksps, while an 100...001 FSR = +FS – –FS auto power-down feature is provided to further reduce OUTPUT CODE (TWO’S COMPLEMENT) 100...000 1LSB = FSR/262144 power dissipation during inactive periods. –FSR/2 –1 0V 1 FSR/2 – 1LSB LSB LSB The LTC2377-18 features a unique digital gain compres- INPUT VOLTAGE (V) 237718 F02 sion (DGC) function, which eliminates the driver amplifier’s
Figure 2. LTC2377-18 Transfer Function
negative supply while preserving the full resolution of the ADC. When enabled, the ADC performs a digital scaling
ANALOG INPUT
function that maps zero-scale code from 0V to 0.1 • VREF The analog inputs of the LTC2377-18 are fully differential and full-scale code from VREF to 0.9 • VREF. For a typical in order to maximize the signal swing that can be digitized. reference voltage of 5V, the full-scale input range is now The analog inputs can be modeled by the equivalent circuit 0.5V to 4.5V, which provides adequate headroom for shown in Figure 3. The diodes at the input provide ESD powering the driving amplifier from a single 5.5V supply. protection. In the acquisition phase, each input sees ap- proximately 45pF (CIN) from the sampling CDAC in series
CONVERTER OPERATION
with 40Ω (RON) from the on-resistance of the sampling switch. Any unwanted signal that is common to both The LTC2377-18 operates in two phases. During the ac- inputs will be reduced by the common mode rejection of quisition phase, the charge redistribution capacitor D/A the ADC. The inputs draw a current spike while charging converter (CDAC) is connected to the IN+ and IN– pins to the CIN capacitors during acquisition. During conversion, sample the differential analog input voltage. A rising edge the analog inputs draw only a small leakage current. on the CNV pin initiates a conversion. During the conversion phase, the 18-bit CDAC is sequenced through a succes- REF C R IN sive approximation algorithm, effectively comparing the ON 45pF 40Ω sampled input with binary-weighted fractions of the refer- IN+ ence voltage (e.g. VREF/2, VREF/4 … VREF/262144) using the differential comparator. At the end of conversion, the BIAS REF VOLTAGE CDAC output approximates the sampled analog input. The C R IN ON 45pF ADC control logic then prepares the 18-bit digital output 40Ω IN– code for serial transfer. 237718 F03
Figure 3. The Equivalent Circuit for the Differential Analog Input of the LTC2377-18
237718fa 10 For more information www.linear.com/LTC2377-18 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Converter Characteristics Dynamic Accuracy Reference Input Digital Inputs and Digital Outputs Power Requirements ADC Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagram Applications Information Board Layout Package Description Revision History Typical Application Related Parts