Datasheet LTC2369-18 (Analog Devices) - 10

LTC2369-18
APPLICATIONS INFORMATION OVERVIEW
1LSB = FS/262144 111...111 The LTC2369-18 is a low noise, low power, high speed 18-bit 111...110 successive approximation register (SAR) ADC. Operating 111...101 from a single 2.5V supply, the LTC2369-18 supports a 111...100 0V to VREF pseudo-differential unipolar input range with VREF ranging from 2.5V to 5.1V, making it ideal for high OUTPUT CODE UNIPOLAR performance applications which require a wide dynamic ZERO 000...011 range. The LTC2369-18 achieves ±2.5LSB INL max, no 000...010 missing codes at 18 bits and 96.5dB SNR. 000...001 000...000 Fast 1.6Msps throughput with no cycle latency makes 0V 1 FS – 1LSB LSB the LTC2369-18 ideally suited for a wide variety of high INPUT VOLTAGE (V) 236918 F02 speed applications. An internal oscillator sets the con-
Figure 2. LTC2369-18 Transfer Function
version time, easing external timing considerations. The LTC2369-18 dissipates only 18mW at 1.6Msps, while an
ANALOG INPUT
auto power-down feature is provided to further reduce The analog inputs of the LTC2369-18 are pseudo-differential power dissipation during inactive periods. in order to reduce any unwanted signal that is common to both inputs. The analog inputs can be modeled by the
CONVERTER OPERATION
equivalent circuit shown in Figure 3. The diodes at the input provide ESD protection. In the acquisition phase, each The LTC2369-18 operates in two phases. During the ac- input sees approximately 45pF (CIN) from the sampling quisition phase, the charge redistribution capacitor D/A CDAC in series with 40Ω (RON) from the on-resistance converter (CDAC) is connected to the IN+ and IN– pins to of the sampling switch. The IN+ input draws a current sample the pseudo-differential analog input voltage. A ris- spike while charging the CIN capacitor during acquisition. ing edge on the CNV pin initiates a conversion. During the During conversion, the analog inputs draw only a small conversion phase, the 18-bit CDAC is sequenced through a leakage current. successive approximation algorithm, effectively comparing the sampled input with binary-weighted fractions of the REF CIN reference voltage (e.g. V R REF/2, VREF/4 … VREF/262144) ON 45pF 40Ω using the differential comparator. At the end of conver- IN+ sion, the CDAC output approximates the sampled analog input. The ADC control logic then prepares the 18-bit BIAS digital output code for serial transfer. REF VOLTAGE CIN RON 45pF 40Ω IN– 236918 F03
TRANSFER FUNCTION
The LTC2369-18 digitizes the full-scale voltage of REF into 218 levels, resulting in an LSB size of 19μV with
Figure 3. The Equivalent Circuit for the
REF = 5V. The ideal transfer function is shown in Figure 2.
Differential Analog Input of the LTC2369-18
The output data is in straight binary format. 236918fa 10