Datasheet LTC2368-24 (Analog Devices) - 5
| Hersteller | Analog Devices |
| Beschreibung | 24-Bit, 1Msps, Pseudo- Differential Unipolar SAR ADC with Integrated Digital Filter |
| Seiten / Seite | 30 / 5 — ADC. TIMING CHARACTERISTICSThe. denotes the specifications which apply … |
| Dateiformat / Größe | PDF / 1.1 Mb |
| Dokumentensprache | Englisch |
ADC. TIMING CHARACTERISTICSThe. denotes the specifications which apply over the full operating
Modelllinie für dieses Datenblatt
- LTC2368CDE-24#PBF LTC2368CDE-24#PBF LTC2368CDE-24#TRPBF LTC2368CDE-24#TRPBF LTC2368CMS-24#PBF LTC2368CMS-24#PBF LTC2368CMS-24#TRPBF LTC2368CMS-24#TRPBF LTC2368IDE-24#PBF LTC2368IDE-24#PBF LTC2368IDE-24#TRPBF LTC2368IDE-24#TRPBF LTC2368IMS-24#PBF LTC2368IMS-24#PBF LTC2368IMS-24#TRPBF LTC2368IMS-24#TRPBF
Textversion des Dokuments
LTC2368-24
ADC TIMING CHARACTERISTICSThe
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
tACQ Acquisition Time tACQ = tCYC – tCONV – tBUSYLH (Note 7) l 312 ns tCYC Time Between Conversions l 1 µs tCNVH CNV High Time l 20 ns tCNVL Minimum Low Time for CNV (Note 11) l 20 ns tBUSYLH CNV↑ to BUSY↑ Delay CL = 20pF l 13 ns tQUIET SCK Quiet Time from CNV↑ (Note 7) l 10 ns tSCK SCK Period (Notes 11, 12) l 10 ns tSCKH SCK High Time l 4 ns tSCKL SCK Low Time l 4 ns tSSDISCK SDI Setup Time From SCK↑ (Note 11) l 4 ns tHSDISCK SDI Hold Time From SCK↑ (Note 11) l 1 ns tSCKCH SCK Period in Chain Mode tSCKCH = tSSDISCK + tDSDO (Note 11) l 13.5 ns tDSDO SDO Data Valid Delay from SCK↑ CL = 20pF, OVDD = 5.25V l 7.5 ns CL = 20pF, OVDD = 2.5V l 8 ns CL = 20pF, OVDD = 1.71V l 9.5 ns tHSDO SDO Data Remains Valid Delay from SCK↑ CL = 20pF (Note 7) l 1 ns tDSDOBUSYL SDO Data Valid Delay from BUSY↓ CL = 20pF (Note 7) l 5 ns tEN Bus Enable Time After RDL↓ (Note 11) l 16 ns tDIS Bus Relinquish Time After RDL↑ (Note 11) l 13 ns
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 7:
Guaranteed by design, not subject to test. may cause permanent damage to the device. Exposure to any Absolute
Note 8:
Zero-scale error is the offset voltage measured from 0.5LSB when Maximum Rating condition for extended periods may affect device the output code flickers between 0000 0000 0000 0000 0000 0000 and reliability and lifetime. 0000 0000 0000 0000 0000 0001. Full-scale error is the deviation of the
Note 2:
All voltage values are with respect to ground. last code transition from ideal and includes the effect of offset error.
Note 3:
When these pin voltages are taken below ground or above REF or
Note 9:
All specifications in dB are referred to a full-scale 5V input with a OVDD, they will be clamped by internal diodes. This product can handle 5V reference voltage, unless otherwise specified. input currents up to 100mA below ground or above REF or OVDD without
Note 10:
fSMPL = 1MHz, IREF varies proportionally with sample rate. latchup.
Note 11:
Parameter tested and guaranteed at OVDD = 1.71V, OVDD = 2.5V
Note 4:
VDD = 2.5V, OVDD = 2.5V, REF = 5V, fSMPL = 1MHz, N = 1. and OVDD = 5.25V.
Note 5:
Recommended operating conditions.
Note 12:
tSCK of 10ns maximum allows a shift clock frequency up to
Note 6:
Integral nonlinearity is defined as the deviation of a code from a 100MHz for rising edge capture. straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. 0.8 • OVDD tWIDTH 0.2 • OVDD t tDELAY 50% 50% DELAY 236824 F01 0.8 • OVDD 0.8 • OVDD 0.2 • OVDD 0.2 • OVDD
Figure 1. Voltage Levels for Timing Specifications
236824f For more information www.linear.com/LTC2368-24 5 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Converter Characteristics Dynamic Accuracy Reference Input Digital Inputs and Digital Outputs Power Requirements ADC Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagram Applications Information Package Description Typical Application Related Parts
ADC TIMING CHARACTERISTICSThe
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
tACQ Acquisition Time tACQ = tCYC – tCONV – tBUSYLH (Note 7) l 312 ns tCYC Time Between Conversions l 1 µs tCNVH CNV High Time l 20 ns tCNVL Minimum Low Time for CNV (Note 11) l 20 ns tBUSYLH CNV↑ to BUSY↑ Delay CL = 20pF l 13 ns tQUIET SCK Quiet Time from CNV↑ (Note 7) l 10 ns tSCK SCK Period (Notes 11, 12) l 10 ns tSCKH SCK High Time l 4 ns tSCKL SCK Low Time l 4 ns tSSDISCK SDI Setup Time From SCK↑ (Note 11) l 4 ns tHSDISCK SDI Hold Time From SCK↑ (Note 11) l 1 ns tSCKCH SCK Period in Chain Mode tSCKCH = tSSDISCK + tDSDO (Note 11) l 13.5 ns tDSDO SDO Data Valid Delay from SCK↑ CL = 20pF, OVDD = 5.25V l 7.5 ns CL = 20pF, OVDD = 2.5V l 8 ns CL = 20pF, OVDD = 1.71V l 9.5 ns tHSDO SDO Data Remains Valid Delay from SCK↑ CL = 20pF (Note 7) l 1 ns tDSDOBUSYL SDO Data Valid Delay from BUSY↓ CL = 20pF (Note 7) l 5 ns tEN Bus Enable Time After RDL↓ (Note 11) l 16 ns tDIS Bus Relinquish Time After RDL↑ (Note 11) l 13 ns
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 7:
Guaranteed by design, not subject to test. may cause permanent damage to the device. Exposure to any Absolute
Note 8:
Zero-scale error is the offset voltage measured from 0.5LSB when Maximum Rating condition for extended periods may affect device the output code flickers between 0000 0000 0000 0000 0000 0000 and reliability and lifetime. 0000 0000 0000 0000 0000 0001. Full-scale error is the deviation of the
Note 2:
All voltage values are with respect to ground. last code transition from ideal and includes the effect of offset error.
Note 3:
When these pin voltages are taken below ground or above REF or
Note 9:
All specifications in dB are referred to a full-scale 5V input with a OVDD, they will be clamped by internal diodes. This product can handle 5V reference voltage, unless otherwise specified. input currents up to 100mA below ground or above REF or OVDD without
Note 10:
fSMPL = 1MHz, IREF varies proportionally with sample rate. latchup.
Note 11:
Parameter tested and guaranteed at OVDD = 1.71V, OVDD = 2.5V
Note 4:
VDD = 2.5V, OVDD = 2.5V, REF = 5V, fSMPL = 1MHz, N = 1. and OVDD = 5.25V.
Note 5:
Recommended operating conditions.
Note 12:
tSCK of 10ns maximum allows a shift clock frequency up to
Note 6:
Integral nonlinearity is defined as the deviation of a code from a 100MHz for rising edge capture. straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. 0.8 • OVDD tWIDTH 0.2 • OVDD t tDELAY 50% 50% DELAY 236824 F01 0.8 • OVDD 0.8 • OVDD 0.2 • OVDD 0.2 • OVDD
Figure 1. Voltage Levels for Timing Specifications
236824f For more information www.linear.com/LTC2368-24 5 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Converter Characteristics Dynamic Accuracy Reference Input Digital Inputs and Digital Outputs Power Requirements ADC Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagram Applications Information Package Description Typical Application Related Parts