Datasheet LTC2351-14 (Analog Devices) - 4

LTC2351-14
DIGITAL INPUTS AND DIGITAL OUTPUTS The
l
denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. VDD = VCC = 3V.
IIN Digital Input Current VIN = 0V to VDD l ±10 μA CIN Digital Input Capacitance 5 pF VOH High Level Output Voltage VDD = 3V, IOUT = –200μA l 2.5 2.9 V VOL Low Level Output Voltage VDD = 2.7V, IOUT= 160μA 0.05 V VDD = 2.7V, IOUT = 1.6mA l 0.4 V IOZ Hi-Z Output Leakage DOUT VOUT = 0V and VDD l ±10 μA COZ Hi-Z Output Capacitance DOUT 1 pF ISOURCE Output Short-Circuit Source Current VOUT = 0V, VDD = 3V 20 mA ISINK Output Short-Circuit Sink Current VOUT = VDD = 3V 15 mA
POWER REQUIREMENTS The
l
denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. VDD = VCC = 3V. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VDD, VCC Supply Voltage 2.7 3 3.6 V IDD + ICC Supply Current Active Mode, fSAMPLE = 1.5Msps l 5.5 8 mA Nap Mode l 1.5 2 mA Active Mode, fSAMPLE = 1.5Msps (LTC2351H-14) l 6 9 mA Nap Mode (LTC2351H-14) l 1.8 2.5 mA Sleep Mode 4 15 μA PD Power Dissipation Active Mode with SCK, fSAMPLE = 1.5Msps 16.5 mW
TIMING CHARACTERISTICS The
l
denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. VDD = 3V. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSAMPLE(MAX) Maximum Sampling Rate per Channel l 250 kHz (Conversion Rate) tTHROUGHPUT Minimum Sampling Period (Conversion + Acquisiton Period) l 4 μs tSCK Clock Period (Note 16) l 40 10000 ns tCONV Conversion Time (Notes 6, 17) 96 SCLK cycles t1 Minimum High or Low SCLK Pulse Width (Note 6) 2 ns t2 CONV to SCK Setup Time (Notes 6, 10) 3 10000 ns t3 SCK Before CONV (Note 6) 0 ns t4 Minimum High or Low CONV Pulse Width (Note 6) 4 ns t5 SCK↑ to Sample Mode (Note 6) 4 ns t6 CONV↑ to Hold Mode (Notes 6, 11) 1.2 ns t7 96th SCK↑ to CONV↑ Interval (Affects Acquisition Period) (Notes 6, 7, 13) 45 ns t8 Minimum Delay from SCK to Valid Bits 0 Through 11 (Notes 6, 12) 8 ns t9 SCK↑ to Hi-Z at SDO (Notes 6, 12) 6 ns t10 Previous SDO Bit Remains Valid After SCK (Notes 6, 12) 2 ns t11 VREF Settling Time After Sleep-to-Wake Transition (Notes 6, 14) 2 ms
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 3:
When these pins are taken below GND or above VDD, they will be may cause permanent damage to the device. Exposure to any Absolute clamped by internal diodes. This product can handle input currents greater Maximum Rating condition for extended periods may affect device than 100mA below GND or greater than VDD without latchup. reliabilty and lifetime.
Note 4:
Offset and range specifi cations apply for a single-ended CH0+ – CH5+
Note 2:
All voltage values are with respect to ground GND. input with CH0– – CH5– grounded and using the internal 2.5V reference. 235114fb 4