Datasheet LTC2348-16 (Analog Devices) - 8
| Hersteller | Analog Devices |
| Beschreibung | Octal, 16-Bit, 200ksps Differential ±10.24V Input SoftSpan ADC with Wide Input Common Mode Range |
| Seiten / Seite | 40 / 8 — aDc TiMing characTerisTics. Note 1:. Note 10:. Note 11:. Note 2:. Note … |
| Dateiformat / Größe | PDF / 1.5 Mb |
| Dokumentensprache | Englisch |
aDc TiMing characTerisTics. Note 1:. Note 10:. Note 11:. Note 2:. Note 12:. Note 3:. Note 4:. Note 5:. Note 13:. Note 6:. Note 14:. Note 7:
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Textversion des Dokuments
LTC2348-16
aDc TiMing characTerisTics Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 10:
Integral nonlinearity is defined as the deviation of a code from a may cause permanent damage to the device. Exposure to any Absolute straight line passing through the actual endpoints of the transfer curve. Maximum Rating condition for extended periods may affect device The deviation is measured from the center of the quantization band. reliability and lifetime.
Note 11:
Guaranteed by design, not subject to test.
Note 2:
All voltage values are with respect to ground.
Note 12:
For bipolar SoftSpan ranges 7, 6, 3, and 2, zero-scale error is
Note 3:
VDDLBYP is the output of an internal voltage regulator, and should the offset voltage measured from –0.5LSB when the output code flickers only be connected to a 2.2μF ceramic capacitor to bypass the pin to GND, between 0000 0000 0000 0000 and 1111 1111 1111 1111. Full-scale as described in the Pin Functions section. Do not connect this pin to any error for these SoftSpan ranges is the worst-case deviation of the first and external circuitry. last code transitions from ideal and includes the effect of offset error. For
Note 4:
When these pin voltages are taken below V unipolar SoftSpan ranges 5, 4, and 1, zero-scale error is the offset voltage EE or above VCC, they will be clamped by internal diodes. This product can handle input currents measured from 0.5LSB when the output code flickers between 0000 0000 of up to 100mA below V 0000 0000 and 0000 0000 0000 0001. Full-scale error for these SoftSpan EE or above VCC without latch-up.
Note 5:
When these pin voltages are taken below ground or above V ranges is the worst-case deviation of the last code transition from ideal DD or OV and includes the effect of offset error. DD, they will be clamped by internal diodes. This product can handle currents of up to 100mA below ground or above V
Note 13:
All specifications in dB are referred to a full-scale input in the DD or OVDD without latch-up. relevant SoftSpan input range, except for crosstalk, which is referred to
Note 6:
–16.5V ≤ V the crosstalk injection signal amplitude. EE ≤ 0V, 0V ≤ VCC ≤ 38V, 10V ≤ (VCC – VEE) ≤ 38V, V
Note 14:
Temperature coefficient is calculated by dividing the maximum DD = 5V, unless otherwise specified.
Note 7:
Recommended operating conditions. change in output voltage by the specified temperature range.
Note 8:
Exceeding these limits on any channel may corrupt conversion
Note 15:
When REFBUF is overdriven, the internal reference buffer must results on other channels. Refer to Absolute Maximum Ratings section for be disabled by setting REFIN = 0V. pin voltage limits related to device reliability.
Note 16:
IREFBUF varies proportionally with sample rate and the number of
Note 9:
V active channels. CC = 15V, VEE = –15V, VDD = 5V, OVDD = 2.5V, fSMPL = 200ksps, internal reference and buffer, true bipolar input signal drive in bipolar
Note 17:
Parameter tested and guaranteed at OVDD = 1.71V, OVDD = 2.5V, SoftSpan ranges, unipolar signal drive in unipolar SoftSpan ranges, unless and OVDD = 5.25V. otherwise specified.
Note 18:
A tSCKI period of 10ns minimum allows a shift clock frequency of up to 100MHz for rising edge capture.
Note 19:
VICM = 1.2V, VID = 350mV for LVDS differential input pairs.
CMOS Timings
0.8 • OVDD tWIDTH 0.2 • OVDD t tDELAY 50% 50% DELAY 234816 F01 0.8 • OVDD 0.8 • OVDD 0.2 • OVDD 0.2 • OVDD
LVDS Timings (Differential)
+200mV tWIDTH –200mV t tDELAY 0V 0V DELAY 234816 F01b +200mV +200mV –200mV –200mV
Figure 1. Voltage Levels for Timing Specifications
234816fa 8 For more information www.linear.com/LTC2348-16 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Converter Characteristics Dynamic Accuracy Internal Reference Characteristics Reference Buffer Characteristics Digital Inputs and Digital Outputs Power Requirements ADC Timing Characteristics Typical Performance Characteristics Pin Functions Configuration Tables Functional Block Diagram Timing Diagram Applications Information Board Layout Package Description Revision History Typical Application Related Parts
aDc TiMing characTerisTics Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 10:
Integral nonlinearity is defined as the deviation of a code from a may cause permanent damage to the device. Exposure to any Absolute straight line passing through the actual endpoints of the transfer curve. Maximum Rating condition for extended periods may affect device The deviation is measured from the center of the quantization band. reliability and lifetime.
Note 11:
Guaranteed by design, not subject to test.
Note 2:
All voltage values are with respect to ground.
Note 12:
For bipolar SoftSpan ranges 7, 6, 3, and 2, zero-scale error is
Note 3:
VDDLBYP is the output of an internal voltage regulator, and should the offset voltage measured from –0.5LSB when the output code flickers only be connected to a 2.2μF ceramic capacitor to bypass the pin to GND, between 0000 0000 0000 0000 and 1111 1111 1111 1111. Full-scale as described in the Pin Functions section. Do not connect this pin to any error for these SoftSpan ranges is the worst-case deviation of the first and external circuitry. last code transitions from ideal and includes the effect of offset error. For
Note 4:
When these pin voltages are taken below V unipolar SoftSpan ranges 5, 4, and 1, zero-scale error is the offset voltage EE or above VCC, they will be clamped by internal diodes. This product can handle input currents measured from 0.5LSB when the output code flickers between 0000 0000 of up to 100mA below V 0000 0000 and 0000 0000 0000 0001. Full-scale error for these SoftSpan EE or above VCC without latch-up.
Note 5:
When these pin voltages are taken below ground or above V ranges is the worst-case deviation of the last code transition from ideal DD or OV and includes the effect of offset error. DD, they will be clamped by internal diodes. This product can handle currents of up to 100mA below ground or above V
Note 13:
All specifications in dB are referred to a full-scale input in the DD or OVDD without latch-up. relevant SoftSpan input range, except for crosstalk, which is referred to
Note 6:
–16.5V ≤ V the crosstalk injection signal amplitude. EE ≤ 0V, 0V ≤ VCC ≤ 38V, 10V ≤ (VCC – VEE) ≤ 38V, V
Note 14:
Temperature coefficient is calculated by dividing the maximum DD = 5V, unless otherwise specified.
Note 7:
Recommended operating conditions. change in output voltage by the specified temperature range.
Note 8:
Exceeding these limits on any channel may corrupt conversion
Note 15:
When REFBUF is overdriven, the internal reference buffer must results on other channels. Refer to Absolute Maximum Ratings section for be disabled by setting REFIN = 0V. pin voltage limits related to device reliability.
Note 16:
IREFBUF varies proportionally with sample rate and the number of
Note 9:
V active channels. CC = 15V, VEE = –15V, VDD = 5V, OVDD = 2.5V, fSMPL = 200ksps, internal reference and buffer, true bipolar input signal drive in bipolar
Note 17:
Parameter tested and guaranteed at OVDD = 1.71V, OVDD = 2.5V, SoftSpan ranges, unipolar signal drive in unipolar SoftSpan ranges, unless and OVDD = 5.25V. otherwise specified.
Note 18:
A tSCKI period of 10ns minimum allows a shift clock frequency of up to 100MHz for rising edge capture.
Note 19:
VICM = 1.2V, VID = 350mV for LVDS differential input pairs.
CMOS Timings
0.8 • OVDD tWIDTH 0.2 • OVDD t tDELAY 50% 50% DELAY 234816 F01 0.8 • OVDD 0.8 • OVDD 0.2 • OVDD 0.2 • OVDD
LVDS Timings (Differential)
+200mV tWIDTH –200mV t tDELAY 0V 0V DELAY 234816 F01b +200mV +200mV –200mV –200mV
Figure 1. Voltage Levels for Timing Specifications
234816fa 8 For more information www.linear.com/LTC2348-16 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Converter Characteristics Dynamic Accuracy Internal Reference Characteristics Reference Buffer Characteristics Digital Inputs and Digital Outputs Power Requirements ADC Timing Characteristics Typical Performance Characteristics Pin Functions Configuration Tables Functional Block Diagram Timing Diagram Applications Information Board Layout Package Description Revision History Typical Application Related Parts