Datasheet LTC2326-18 (Analog Devices) - 6
| Hersteller | Analog Devices |
| Beschreibung | 18-Bit, 250ksps, ±10.24V True Bipolar, Pseudo-Differential Input ADC with 95dB SNR |
| Seiten / Seite | 26 / 6 — elecTrical characTerisTics Note 1:. Note 8:. Note 9:. Note 2:. Note 10:. … |
| Dateiformat / Größe | PDF / 518 Kb |
| Dokumentensprache | Englisch |
elecTrical characTerisTics Note 1:. Note 8:. Note 9:. Note 2:. Note 10:. Note 3:. Note 11:. Note 12:. Note 13:. Note 4:. Note 14:. Note 5:
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Textversion des Dokuments
LTC2326-18
elecTrical characTerisTics Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 8:
All specifications in dB are referred to a full-scale ±10.24V input may cause permanent damage to the device. Exposure to any Absolute with REFIN = 2.048V. Maximum Rating condition for extended periods may affect device
Note 9:
When REFBUF is overdriven, the internal reference buffer must be reliability and lifetime. turned off by setting REFIN = 0V.
Note 2:
All voltage values are with respect to ground.
Note 10:
fSMPL = 250kHz, IREFBUF varies proportionally with sample rate.
Note 3:
When these pin voltages are taken below ground or above VDD or
Note 11:
Guaranteed by design, not subject to test. OVDD, they will be clamped by internal diodes. This product can handle
Note 12:
Parameter tested and guaranteed at OV input currents up to 100mA below ground or above V DD = 1.71V, OVDD = 2.5V DD or OVDD without and OV latch-up. DD = 5.25V.
Note 13:
t
Note 4:
V SCK of 10ns maximum allows a shift clock frequency up to DD = 5V, OVDD = 2.5V, ±10.24V Range, REFIN = 2.048V, 100MHz for rising edge capture. fSMPL = 250kHz.
Note 14:
Temperature coefficient is calculated by dividing the maximum
Note 5:
Recommended operating conditions. change in output voltage by the specified temperature range.
Note 6:
Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band.
Note 7:
Bipolar zero error is the offset voltage measured from –0.5LSB when the output code flickers between 00 0000 0000 0000 0000 and 11 1111 1111 1111 1111. Full-scale bipolar error is the worst-case of –FS or +FS untrimmed deviation from ideal first and last code transitions and includes the effect of offset error. 0.8 • OVDD tWIDTH 0.2 • OVDD t tDELAY 50% 50% DELAY 232618 F01 0.8 • OVDD 0.8 • OVDD 0.2 • OVDD 0.2 • OVDD
Figure 1. Voltage Levels for Timing Specifications
232618fb 6 For more information www.linear.com/LTC2326-18 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Converter Characteristics Dynamic Accuracy Internal Reference Characteristics Reference Buffer Characteristics Digital Inputs and Digital Outputs Power Requirements ADC Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagram Applications Information Board Layout Package Description Revision History Typical Application Related Parts
elecTrical characTerisTics Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 8:
All specifications in dB are referred to a full-scale ±10.24V input may cause permanent damage to the device. Exposure to any Absolute with REFIN = 2.048V. Maximum Rating condition for extended periods may affect device
Note 9:
When REFBUF is overdriven, the internal reference buffer must be reliability and lifetime. turned off by setting REFIN = 0V.
Note 2:
All voltage values are with respect to ground.
Note 10:
fSMPL = 250kHz, IREFBUF varies proportionally with sample rate.
Note 3:
When these pin voltages are taken below ground or above VDD or
Note 11:
Guaranteed by design, not subject to test. OVDD, they will be clamped by internal diodes. This product can handle
Note 12:
Parameter tested and guaranteed at OV input currents up to 100mA below ground or above V DD = 1.71V, OVDD = 2.5V DD or OVDD without and OV latch-up. DD = 5.25V.
Note 13:
t
Note 4:
V SCK of 10ns maximum allows a shift clock frequency up to DD = 5V, OVDD = 2.5V, ±10.24V Range, REFIN = 2.048V, 100MHz for rising edge capture. fSMPL = 250kHz.
Note 14:
Temperature coefficient is calculated by dividing the maximum
Note 5:
Recommended operating conditions. change in output voltage by the specified temperature range.
Note 6:
Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band.
Note 7:
Bipolar zero error is the offset voltage measured from –0.5LSB when the output code flickers between 00 0000 0000 0000 0000 and 11 1111 1111 1111 1111. Full-scale bipolar error is the worst-case of –FS or +FS untrimmed deviation from ideal first and last code transitions and includes the effect of offset error. 0.8 • OVDD tWIDTH 0.2 • OVDD t tDELAY 50% 50% DELAY 232618 F01 0.8 • OVDD 0.8 • OVDD 0.2 • OVDD 0.2 • OVDD
Figure 1. Voltage Levels for Timing Specifications
232618fb 6 For more information www.linear.com/LTC2326-18 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Converter Characteristics Dynamic Accuracy Internal Reference Characteristics Reference Buffer Characteristics Digital Inputs and Digital Outputs Power Requirements ADC Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagram Applications Information Board Layout Package Description Revision History Typical Application Related Parts