Datasheet LTC2324-14 (Analog Devices) - 10

LTC2324-14
pin FuncTions PINS THAT ARE THE SAME FOR ALL DIGITAL I/O MODES REFOUT1 (Pin 22):
Reference Buffer 1 Output. An onboard buffer nominally outputs 4.096V to this pin. This pin is
AIN4+, AIN4– (Pins 2, 1):
Analog Differential Input Pins. referred to GND and should be decoupled closely to the Full-scale range (AIN4+ – AIN4–) is ±REFOUT4 voltage. pin with a 10µF (X5R, 0805 size) ceramic capacitor. The These pins can be driven from VDD to GND. internal buffer driving this pin may be disabled by ground-
GND (Pins 3, 7, 12, 18, 26, 32, 38, 46, 49):
Ground. ing the REFBUFEN pin. If the buffer is disabled, an external These pins and exposed pad (Pin 53) must be tied directly reference may drive this pin in the range of 1.25V to 5V. to a solid ground plane.
SDR
/
DDR (Pin 23):
Double Data Rate Input. Controls the
AIN3+, AIN3– (Pins 5, 4):
Analog Differential Input Pins. frequency of SCK and CLKOUT. Tie to GND for the falling Full-scale range (AIN3+ – AIN3–) is ±REFOUT3 voltage. edge of SCK to shift each serial data output (Single Data These pins can be driven from VDD to GND. Rate, SDR). Tie to OVDD to shift serial data output on each edge of SCK (Double Data Rate, DDR). CLKOUT will be a
REFOUT3 (Pin 6):
Reference Buffer 3 Output. An onboard delayed version of SCK for both pin states. buffer nominally outputs 4.096V to this pin. This pin is referred to GND and should be decoupled closely to the
CNV (Pin 24):
Convert Input. This pin, when high, defines pin with a 10µF (X5R, 0805 size) ceramic capacitor. The the acquisition phase. When this pin is driven low, the internal buffer driving this pin may be disabled by ground- conversion phase is initiated and output data is clocked ing the REFBUFEN pin. If the buffer is disabled, an external out. This input must be driven at OVDD levels with a low reference may drive this pin in the range of 1.25V to 5V. jitter pulse. This pin is unaffected by the CMOS/LVDS pin.
REF (Pin 8):
Common 4.096V reference output. Decouple
CMOS/LVDS (Pin 25):
I/O Mode Select. Ground this pin to GND with a 1μF low ESR ceramic capacitor. May be to enable CMOS mode, tie to OVDD to enable LVDS mode. overdriven with a single external reference to establish a Float this pin to enable low power LVDS mode. common reference for ADC cores 1 through 4.
OVDD (Pins 31, 37):
I/O Interface Digital Power. The range
REFOUT2 (Pin 9):
Reference Buffer 2 Output. An onboard of OVDD is 1.71V to 2.63V. This supply is nominally set buffer nominally outputs 4.096V to this pin. This pin is to the same supply as the host interface (CMOS: 1.8V or referred to GND and should be decoupled closely to the 2.5V, LVDS: 2.5V). Bypass OVDD to GND (Pins 32 and 38) pin with a 10µF (X5R, 0805 size) ceramic capacitor. The with 0.1µF capacitors. internal buffer driving this pin may be disabled by ground-
REFBUFEN (Pin 43):
Reference Buffer Output Enable. Tie ing the REFBUFEN pin. If the buffer is disabled, an external to V reference may drive this pin in the range of 1.25V to 5V. DD when using the internal reference. Tie to ground to disable the internal REFOUT1–4 buffers for use with
AIN2+, AIN2– (Pins 11, 10):
Analog Differential Input Pins. external voltage references. This pin has a 500k internal Full-scale range (AIN2+ – AIN2–) is ±REFOUT2 voltage. pull-up to VDD. These pins can be driven from VDD to GND.
REFOUT4 (Pin 45):
Reference Buffer 4 Output. An onboard
AIN1+, AIN1– (Pins 14, 13):
Analog Differential Input Pins. buffer nominally outputs 4.096V to this pin. This pin is Full-scale range (AIN1+ – AIN1–) is ±REFOUT1 voltage. referred to GND and should be decoupled closely to the These pins can be driven from VDD to GND. pin with a 10µF (X5R, 0805 size) ceramic capacitor. The internal buffer driving this pin may be disabled by ground-
VDD (Pins 15, 21, 44, 52):
Power Supply. Bypass VDD to ing the REFBUFEN pin. If the buffer is disabled, an external GND with a 10µF ceramic capacitor and a 0.1µF ceramic reference may drive this pin in the range of 1.25V to 5V. capacitor close to the part. The VDD pins should be shorted together and driven from the same supply.
Exposed Pad (Pin 53):
Ground. Solder this pad to ground. 232414f 10 For more information www.linear.com/LTC2324-14 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Converter Characteristics Dynamic Accuracy Internal Reference Characteristics Digital Inputs And Digital Outputs Power Requirements ADC Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagram Applications Information Package Description Related Parts Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Converter Characteristics Dynamic Accuracy Internal Reference Characteristics Digital Inputs And Digital Outputs Power Requirements ADC Timing Characteristics ADC Timing Characteristics ADC Timing Characteristics Typical Performance Characteristics Pin Functions Pins that are the same for all digital I/O Modes CMOS data output option (CMOS/LVDS = low) LVDS data output option (CMOS/LVDS = high or FLOAT) Functional Block Diagram Timing Diagram Applications Information OVERVIEW CONVERTER OPERATION TRANSFER FUNCTION INPUT DRIVE CIRCUITS ADC REFERENCE DYNAMIC PERFORMANCE POWER CONSIDERATIONS TIMING AND CONTROL DIGITAL INTERFACE BOARD LAYOUT Package Description Typical Application Related Parts