Datasheet LTC2315-12 (Analog Devices) - 9
| Hersteller | Analog Devices |
| Beschreibung | 12-Bit, 5Msps Serial Sampling ADC in TSOT |
| Seiten / Seite | 22 / 9 — BLOCK DIAGRAM. TIMING DIAGRAMS. Figure 1. SDO Into Hi-Z after 16TH SCK. … |
| Dateiformat / Größe | PDF / 706 Kb |
| Dokumentensprache | Englisch |
BLOCK DIAGRAM. TIMING DIAGRAMS. Figure 1. SDO Into Hi-Z after 16TH SCK. Figure 2. SDO Into Hi-Z after CS
Modelllinie für dieses Datenblatt
- LTC2315CTS8-12#PBF LTC2315CTS8-12#TRMPBF LTC2315CTS8-12#TRMPBF LTC2315CTS8-12#TRPBF LTC2315CTS8-12#TRPBF LTC2315HTS8-12#PBF LTC2315HTS8-12#TRMPBF LTC2315HTS8-12#TRMPBF LTC2315HTS8-12#TRPBF LTC2315HTS8-12#TRPBF LTC2315ITS8-12#PBF LTC2315ITS8-12#TRMPBF LTC2315ITS8-12#TRMPBF LTC2315ITS8-12#TRPBF LTC2315ITS8-12#TRPBF
Textversion des Dokuments
LTC2315-12
BLOCK DIAGRAM
2.2µF 2.2µF ANALOG SUPPLY DIGITAL SUPPLY RANGE 2.7V TO 5.25V RANGE 1.71V TO 5.25V 1 5 VDD OVDD 2.5V LDO A ANALOG IN INPUT RANGE 4 + THREE-STATE SDO 0V TO VREF SERIAL S/H 12-BIT SAR ADC 6 OUTPUT – PORT REF SCK 2 7 TIMING 2.2µF GND 1.024V CS 2×/4× LOGIC 3 BANDGAP 8 TS8 PACKAGE 231512 BD ALL CAPACITORS UNLESS NOTED ARE HIGH QUALITY, CERAMIC CHIP TYPE
TIMING DIAGRAMS
16TH EDGE t8 t9 SCK CS OVDD/2 OVDD/2 Hi-Z Hi-Z SDO SDO
Figure 1. SDO Into Hi-Z after 16TH SCK
↓
Figure 2. SDO Into Hi-Z after CS
↑ 231512 TD01 231512 TD02 t7 t4 SCK SCK OVDD/2 OVDD/2 V V OH OH SDO V SDO OL VOL
Figure 3. SDO Data Valid Hold after SCK
↓
Figure 4. SDO Data Valid Access after SCK
↓ 231512 TD03 231512 TD04 t CS 10 tCONV = 13.5 • tSCK + t2 + t10 tACQ-MIN = 40ns tCONV tACQ-MIN t2 t6 1 2 3 4 12 13 14 SCK t5 t3 t4 t7 t9 SDO 0 B11* B10 B9 B0 0 HI-Z STATE (MSB) tTHROUGHPUT *NOTE: SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION 231512 TD05
Figure 5: LTC2315-12 Serial Interface Timing Diagram (SCK Low During tACQ)
231512fa For more information www.linear.com/LTC2315-12 9
BLOCK DIAGRAM
2.2µF 2.2µF ANALOG SUPPLY DIGITAL SUPPLY RANGE 2.7V TO 5.25V RANGE 1.71V TO 5.25V 1 5 VDD OVDD 2.5V LDO A ANALOG IN INPUT RANGE 4 + THREE-STATE SDO 0V TO VREF SERIAL S/H 12-BIT SAR ADC 6 OUTPUT – PORT REF SCK 2 7 TIMING 2.2µF GND 1.024V CS 2×/4× LOGIC 3 BANDGAP 8 TS8 PACKAGE 231512 BD ALL CAPACITORS UNLESS NOTED ARE HIGH QUALITY, CERAMIC CHIP TYPE
TIMING DIAGRAMS
16TH EDGE t8 t9 SCK CS OVDD/2 OVDD/2 Hi-Z Hi-Z SDO SDO
Figure 1. SDO Into Hi-Z after 16TH SCK
↓
Figure 2. SDO Into Hi-Z after CS
↑ 231512 TD01 231512 TD02 t7 t4 SCK SCK OVDD/2 OVDD/2 V V OH OH SDO V SDO OL VOL
Figure 3. SDO Data Valid Hold after SCK
↓
Figure 4. SDO Data Valid Access after SCK
↓ 231512 TD03 231512 TD04 t CS 10 tCONV = 13.5 • tSCK + t2 + t10 tACQ-MIN = 40ns tCONV tACQ-MIN t2 t6 1 2 3 4 12 13 14 SCK t5 t3 t4 t7 t9 SDO 0 B11* B10 B9 B0 0 HI-Z STATE (MSB) tTHROUGHPUT *NOTE: SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION 231512 TD05
Figure 5: LTC2315-12 Serial Interface Timing Diagram (SCK Low During tACQ)
231512fa For more information www.linear.com/LTC2315-12 9