Datasheet LTC2310-16 (Analog Devices) - 5
| Hersteller | Analog Devices |
| Beschreibung | 16-Bit, 2Msps Differential Input ADC with Wide Input Common Mode Range |
| Seiten / Seite | 24 / 5 — power requireMenTs. The. denotes the specifications which apply over the … |
| Dateiformat / Größe | PDF / 776 Kb |
| Dokumentensprache | Englisch |
power requireMenTs. The. denotes the specifications which apply over the full operating temperature
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LTC2310-16
power requireMenTs The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C (Note 4). SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VDD Supply Voltage 5V Operation l 4.75 5.25 V 3.3V Operation l 3.13 3.47 V OVDD Supply Voltage l 1.71 2.63 V IVDD Supply Current 2Msps Sample Rate (AIN+ = AIN– = 0V) l 6.8 11 mA INAP Nap Mode Current Conversion Done (IVDD) l 2.8 4 mA ISLEEP Sleep Mode Current VDD = 3.3V, Sleep Mode (IVDD + IOVDD) l 0.1 10 μA
CMOS I/O Mode
IOVDD Supply Current 2Msps Sample Rate (CL = 5pF) l 0.5 1 mA PD_3.3V Power Dissipation VDD = 3.3V 5Msps Sample Rate (AIN+ = AIN– = 0V) 25 mW Nap Mode VDD = 3.3V Conversion Done (IVDD + IOVDD) 7.5 mW Sleep Mode VDD = 3.3V Sleep Mode (IVDD + IOVDD) 0.3 μW PD_5V Power Dissipation VDD = 5V 5Msps Sample Rate (AIN+ = AIN– = 0V) l 35 55 mW Nap Mode VDD = 5V Conversion Done (IVDD + IOVDD) l 14 20 mW Sleep Mode VDD = 5V Sleep Mode (IVDD + IOVDD) l 0.5 40 μW
LVDS I/O Mode
IOVDD Supply Current 2Msps Sample Rate (RL = 100Ω) l 2.7 4 mA PD_3.3V Power Dissipation VDD = 3.3V 5Msps Sample Rate (AIN+ = AIN– = 0V) 30 mW Nap Mode VDD = 3.3V Conversion Done (IVDD + IOVDD) 14 mW Sleep Mode VDD = 3.3V Sleep Mode (IVDD + IOVDD) 0.3 µW PD_5V Power Dissipation VDD = 5V 5Msps Sample Rate (AIN+ = AIN– = 0V) l 40 60 mW Nap Mode VDD = 5V Conversion Done (IVDD + IOVDD) l 20 30 mW Sleep Mode VDD = 5V Sleep Mode (IVDD + IOVDD) l 0.5 50 µW
aDc TiMing characTerisTics The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C (Note 4). SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS CMOS, LVDS I/O Modes
fSMPL Maximum Sampling Frequency l 2 Msps tCYC Time Between Conversions (Note 11) l 500 1000000 ns tACQ Acquisition Time (Note 11) l 280 ns tCONV Conversion Time l 220 ns tREADOUT Readout Time l 250 ns tCNVH CNV High Time l 30 ns tDCNVSCKL SCK Quiet Time from CNV↓ (Note 11) l 220 ns tDSCKHCNVH SCK Delay Time to CNV↑ (Note 11) l 0 ns tSCK SCK Period (Notes 12, 13) l 15.6 ns tSCKH SCK High Time l 5 ns tSCKL SCK Low Time l 5 ns 231016f For more information www.linear.com/LTC2310-16 5 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Electrical Characteristics Converter Characteristics Dynamic Accuracy Internal Reference Characteristics Digital Inputs And Digital Outputs Power Requirements ADC Timing Characteristics Typical Performance Characteristics Functional Block Diagram Timing Diagram Applications Information Package Description Related Parts
power requireMenTs The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C (Note 4). SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VDD Supply Voltage 5V Operation l 4.75 5.25 V 3.3V Operation l 3.13 3.47 V OVDD Supply Voltage l 1.71 2.63 V IVDD Supply Current 2Msps Sample Rate (AIN+ = AIN– = 0V) l 6.8 11 mA INAP Nap Mode Current Conversion Done (IVDD) l 2.8 4 mA ISLEEP Sleep Mode Current VDD = 3.3V, Sleep Mode (IVDD + IOVDD) l 0.1 10 μA
CMOS I/O Mode
IOVDD Supply Current 2Msps Sample Rate (CL = 5pF) l 0.5 1 mA PD_3.3V Power Dissipation VDD = 3.3V 5Msps Sample Rate (AIN+ = AIN– = 0V) 25 mW Nap Mode VDD = 3.3V Conversion Done (IVDD + IOVDD) 7.5 mW Sleep Mode VDD = 3.3V Sleep Mode (IVDD + IOVDD) 0.3 μW PD_5V Power Dissipation VDD = 5V 5Msps Sample Rate (AIN+ = AIN– = 0V) l 35 55 mW Nap Mode VDD = 5V Conversion Done (IVDD + IOVDD) l 14 20 mW Sleep Mode VDD = 5V Sleep Mode (IVDD + IOVDD) l 0.5 40 μW
LVDS I/O Mode
IOVDD Supply Current 2Msps Sample Rate (RL = 100Ω) l 2.7 4 mA PD_3.3V Power Dissipation VDD = 3.3V 5Msps Sample Rate (AIN+ = AIN– = 0V) 30 mW Nap Mode VDD = 3.3V Conversion Done (IVDD + IOVDD) 14 mW Sleep Mode VDD = 3.3V Sleep Mode (IVDD + IOVDD) 0.3 µW PD_5V Power Dissipation VDD = 5V 5Msps Sample Rate (AIN+ = AIN– = 0V) l 40 60 mW Nap Mode VDD = 5V Conversion Done (IVDD + IOVDD) l 20 30 mW Sleep Mode VDD = 5V Sleep Mode (IVDD + IOVDD) l 0.5 50 µW
aDc TiMing characTerisTics The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C (Note 4). SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS CMOS, LVDS I/O Modes
fSMPL Maximum Sampling Frequency l 2 Msps tCYC Time Between Conversions (Note 11) l 500 1000000 ns tACQ Acquisition Time (Note 11) l 280 ns tCONV Conversion Time l 220 ns tREADOUT Readout Time l 250 ns tCNVH CNV High Time l 30 ns tDCNVSCKL SCK Quiet Time from CNV↓ (Note 11) l 220 ns tDSCKHCNVH SCK Delay Time to CNV↑ (Note 11) l 0 ns tSCK SCK Period (Notes 12, 13) l 15.6 ns tSCKH SCK High Time l 5 ns tSCKL SCK Low Time l 5 ns 231016f For more information www.linear.com/LTC2310-16 5 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Electrical Characteristics Converter Characteristics Dynamic Accuracy Internal Reference Characteristics Digital Inputs And Digital Outputs Power Requirements ADC Timing Characteristics Typical Performance Characteristics Functional Block Diagram Timing Diagram Applications Information Package Description Related Parts