Datasheet LTC2293, LTC2292, LTC2291 (Analog Devices) - 5

HerstellerAnalog Devices
BeschreibungDual 12-Bit, 65Msps Low Power 3V ADCs
Seiten / Seite28 / 5 — POWER REQUIRE E TS The. denotes the specifications which apply over the …
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POWER REQUIRE E TS The. denotes the specifications which apply over the full operating temperature

POWER REQUIRE E TS The denotes the specifications which apply over the full operating temperature

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LTC2293/LTC2292/LTC2291
W U POWER REQUIRE E TS The

denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25
°
C. (Note 8) LTC2293 LTC2292 LTC2291 SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
VDD Analog Supply (Note 9) ● 2.7 3 3.4 2.7 3 3.4 2.7 3 3.4 V Voltage OVDD Output Supply (Note 9) ● 0.5 3 3.6 0.5 3 3.6 0.5 3 3.6 V Voltage IVDD Supply Current Both ADCs at fS(MAX) ● 133 150 78 95 50 60 mA PDISS Power Dissipation Both ADCs at fS(MAX) ● 400 450 235 285 150 180 mW PSHDN Shutdown Power SHDN = H, 2 2 2 mW (Each Channel) OE = H, No CLK PNAP Nap Mode Power SHDN = H, 15 15 15 mW (Each Channel) OE = L, No CLK
W U TI I G CHARACTERISTICS The

denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25
°
C. (Note 4) LTC2293 LTC2292 LTC2291 SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
fs Sampling Frequency (Note 9) ● 1 65 1 40 1 25 MHz tL CLK Low Time Duty Cycle Stabilizer Off ● 7.3 7.7 500 11.8 12.5 500 18.9 20 500 ns Duty Cycle Stabilizer On ● 5 7.7 500 5 12.5 500 5 20 500 ns (Note 7) tH CLK High Time Duty Cycle Stabilizer Off ● 7.3 7.7 500 11.8 12.5 500 18.9 20 500 ns Duty Cycle Stabilizer On ● 5 7.7 500 5 12.5 500 5 20 500 ns (Note 7) tAP Sample-and-Hold 0 0 0 ns Aperture Delay tD CLK to DATA Delay CL = 5pF (Note 7) ● 1.4 2.7 5.4 1.4 2.7 5.4 1.4 2.7 5.4 ns tMD MUX to DATA Delay CL = 5pF (Note 7) ● 1.4 2.7 5.4 1.4 2.7 5.4 1.4 2.7 5.4 ns Data Access Time CL = 5pF (Note 7) ● 4.3 10 4.3 10 4.3 10 ns After OE↓ BUS Relinquish Time (Note 7) ● 3.3 8.5 3.3 8.5 3.3 8.5 ns Pipeline 5 5 5 Cycles Latency
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 5:
Integral nonlinearity is defined as the deviation of a code from a may cause permanent damage to the device. Exposure to any Absolute straight line passing through the actual endpoints of the transfer curve. Maximum Rating condition for extended periods may affect device The deviation is measured from the center of the quantization band. reliability and lifetime.
Note 6:
Offset error is the offset voltage measured from –0.5 LSB when
Note 2:
All voltage values are with respect to ground with GND and OGND the output code flickers between 0000 0000 0000 and 1111 1111 1111. wired together (unless otherwise noted).
Note 7:
Guaranteed by design, not subject to test.
Note 3:
When these pin voltages are taken below GND or above VDD, they
Note 8:
VDD = 3V, fSAMPLE = 65MHz (LTC2293), 40MHz (LTC2292), or will be clamped by internal diodes. This product can handle input currents 25MHz (LTC2291), input range = 1VP-P with differential drive. The supply of greater than 100mA below GND or above VDD without latchup. current and power dissipation are the sum total for both channels with
Note 4:
VDD = 3V, fSAMPLE = 65MHz (LTC2293), 40MHz (LTC2292), or both channels active. 25MHz (LTC2291), input range = 2VP-P with differential drive, unless
Note 9:
Recommended operating conditions. otherwise noted. 229321fa 5