Datasheet LTC2285 (Analog Devices) - 8

LTC2285
PIN FUNCTIONS A + INA (Pin 1):
Channel A Positive Differential Analog and a ±1V input range. An external reference greater than Input. 0.5V and less than 1V applied to SENSEB selects an input range of ±V
A –
SENSEB. ±1V is the largest valid input range.
INA (Pin 2):
Channel A Negative Differential Analog Input.
VCMB (Pin 20):
Channel B 1.5V Output and Input Common Mode Bias. Bypass to ground with 2.2μF ceramic chip
REFHA (Pins 3, 4):
Channel A High Reference. Short to- capacitor. Do not connect to V gether and bypass to Pins 5, 6 with a 0.1μF ceramic chip CMA. capacitor as close to the pin as possible. Also bypass to
MUX (Pin 21):
Digital Output Multiplexer Control. If MUX Pins 5, 6 with an additional 2.2μF ceramic chip capacitor is High, Channel A comes out on DA0-DA13; Channel B and to ground with a 1μF ceramic chip capacitor. comes out on DB0-DB13. If MUX is Low, the output bus- ses are swapped and Channel A comes out on DB0-DB13;
REFLA (Pins 5, 6):
Channel A Low Reference. Short to- Channel B comes out on DA0-DA13. To multiplex both gether and bypass to Pins 3, 4 with a 0.1μF ceramic chip channels onto a single output bus, connect MUX, CLKA capacitor as close to the pin as possible. Also bypass to and CLKB together. (This is not recommended at clock Pins 3, 4 with an additional 2.2μF ceramic chip capacitor frequencies above 80Msps.) and to ground with a 1μF ceramic chip capacitor.
SHDNB (Pin 22):
Channel B Shutdown Mode Selection
VDD (Pins 7, 10, 18, 63):
Analog 3V Supply. Bypass to Pin. Connecting SHDNB to GND and OEB to GND results GND with 0.1μF ceramic chip capacitors. in normal operation with the outputs enabled. Connecting
CLKA (Pin 8):
Channel A Clock Input. The input sample SHDNB to GND and OEB to VDD results in normal operation starts on the positive edge. with the outputs at high impedance. Connecting SHDNB
CLKB (Pin 9):
Channel B Clock Input. The input sample to VDD and OEB to GND results in nap mode with the starts on the positive edge. outputs at high impedance. Connecting SHDNB to VDD and OEB to VDD results in sleep mode with the outputs
REFLB (Pins 11, 12):
Channel B Low Reference. Short at high impedance. together and bypass to Pins 13, 14 with a 0.1μF ceramic chip capacitor as close to the pin as possible. Also by-
OEB (Pin 23):
Channel B Output Enable Pin. Refer to pass to Pins 13, 14 with an additional 2.2μF ceramic SHDNB pin function. chip capacitor and to ground with a 1μF ceramic chip
DB0 – DB13 (Pins 24 to 30, 33 to 39):
Channel B Digital capacitor. Outputs. DB13 is the MSB.
REFHB (Pins 13, 14):
Channel B High Reference. Short
OGND (Pins 31, 50):
Output Driver Ground. together and bypass to Pins 11, 12 with a 0.1μF ceramic
OV
chip capacitor as close to the pin as possible. Also by-
DD (Pins 32, 49):
Positive Supply for the Output Drivers. Bypass to ground with 0.1μF ceramic chip capacitor. pass to Pins 11, 12 with an additional 2.2μF ceramic chip capacitor and to ground with a 1μF ceramic chip
CLKOUT (Pin 40):
Data Ready Clock Output. Latch data capacitor. on the falling edge of CLKOUT. CLKOUT is derived from CLKB. Tie CLKA to CLKB for simultaneous operation.
A – INB (Pin 15):
Channel B Negative Differential Analog Input.
DA0 – DA13 (Pins 41 to 48, 51 to 56):
Channel A Digital Outputs. DA13 is the MSB.
A + INB (Pin 16):
Channel B Positive Differential Analog Input.
OF (Pin 57):
Overfl ow/Underfl ow Output. High when an overfl ow or underfl ow has occurred on either channel A
GND (Pins 17, 64):
ADC Power Ground. or channel B.
SENSEB (Pin 19):
Channel B Reference Programming Pin.
OEA (Pin 58):
Channel A Output Enable Pin. Refer to Connecting SENSEB to VCMB selects the internal reference SHDNA pin function. and a ±0.5V input range. VDD selects the internal reference 2285fb 8