Datasheet LTC2271 (Analog Devices) - 6

LTC2271
TIMING CHARACTERISTICS The
l
denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fS Sampling Frequency (Note 10) l 5 20 MHz tENCL ENC Low Time (Note 8) Duty Cycle Stabilizer Off l 23.5 25 100 ns Duty Cycle Stabilizer On l 2 25 100 ns tENCH ENC High Time (Note 8) Duty Cycle Stabilizer Off l 23.5 25 100 ns Duty Cycle Stabilizer On l 2 25 100 ns tAP Sample-and-Hold 0 ns Acquistion Delay Time
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Digital Data Outputs (RTERM = 100Ω Differential, CL = 2pF to GND On Each Output)
tSER Serial Data Bit Period 4-Lane Output Mode 1/(4 • fS) Sec 2-Lane Output Mode 1/(8 • fS) 1-Lane Output Mode 1/(16 • fS) tFRAME FR to DCO Delay (Note 8) l 0.35 • tSER 0.5 • tSER 0.65 • tSER Sec tDATA Data to DCO Delay (Note 8) l 0.35 • tSER 0.5 • tSER 0.65 • tSER Sec tPD Propagation Delay (Note 8) l 0.7n + 2 • tSER 1.1n + 2 • tSER 1.5n + 2 • tSER Sec tr Output Rise Time Data, DCO, FR, 20% to 80% 0.17 ns tf Output Fall Time Data, DCO, FR, 20% to 80% 0.17 ns DCO Cycle-Cycle Jitter tSER = 3.1ns 60 psP-P Pipeline Latency 7 7 Cycles
SPI Port Timing (Note 8)
tSCK SCK Period Write Mode l 40 ns Readback Mode, l 250 ns CSDO = 20pF, RPULLUP = 2k tS CS-to-SCK Setup Time l 5 ns tH SCK-to-CS Setup Time l 5 ns tDS SDI Setup Time l 5 ns tDH SDI Hold Time l 5 ns tDO SCK Falling to SDO Readback Mode, l 125 ns Valid CSDO = 20pF, RPULLUP = 2k
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 6:
Integral nonlinearity is defi ned as the deviation of a code from a may cause permanent damage to the device. Exposure to any Absolute best fi t straight line to the transfer curve. The deviation is measured from Maximum Rating condition for extended periods may affect device the center of the quantization band. reliability and lifetime.
Note 7:
Offset error is the offset voltage measured from –0.5LSB when the
Note 2:
All voltage values are with respect to GND with GND and OGND output code fl ickers between 0000 0000 0000 0000 and 1111 1111 1111 shorted (unless otherwise noted). 1111 in 2’s complement output mode.
Note 3:
When these pin voltages are taken below GND or above VDD, they
Note 8:
Guaranteed by design, not subject to test. will be clamped by internal diodes. This product can handle input currents
Note 9:
VDD = OVDD=1.8V, fSAMPLE = 20MHz, 2-lane output mode, ENC+ of greater than 100mA below GND or above VDD without latchup. = single-ended 1.8V square wave, ENC– = 0V, input range = 2.1VP-P with
Note 4:
When these pin voltages are taken below GND they will be differential drive, unless otherwise noted. The supply current and power clamped by internal diodes. When these pin voltages are taken above VDD dissipation specifi cations are totals for the entire IC, not per channel. they will not be clamped by internal diodes. This product can handle input
Note 10:
Recommended operating conditions. currents of greater than 100mA below GND without latchup.
Note 5:
VDD = OVDD = 1.8V, fSAMPLE = 20MHz, 2-lane output mode, differential ENC+/ENC– = 2VP-P sine wave, input range = 2.1VP-P with differential drive, unless otherwise noted. 2271f 6