Datasheet LTC2262-14 (Analog Devices) - 6
| Hersteller | Analog Devices |
| Beschreibung | 14-Bit, 150Msps Ultralow Power 1.8V ADC |
| Seiten / Seite | 28 / 6 — POWER REQUIREMENTS. The. denotes the specifications which apply over the … |
| Dateiformat / Größe | PDF / 680 Kb |
| Dokumentensprache | Englisch |
POWER REQUIREMENTS. The. denotes the specifications which apply over the full operating temperature
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LTC2262-14
POWER REQUIREMENTS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 9) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS LVDS Output Mode
VDD Analog Supply Voltage (Note 10) l 1.7 1.8 1.9 V OVDD Output Supply Voltage (Note 10) l 1.7 1.9 V IVDD Analog Supply Current Sine Wave Input l 88.1 101.3 mA IOVDD Digital Supply Current Sine Input, 1.75mA Mode l 20.7 23 mA (0VDD = 1.8V) Sine Input, 3.5mA Mode l 40.5 44 mA PDISS Power Dissipation Sine Input, 1.75mA Mode l 196 224 mW Sine Input, 3.5mA Mode l 231 262 mW
All Output Modes
PSLEEP Sleep Mode Power 0.5 mW PNAP Nap Mode Power 9 mW PDIFFCLK Power Increase with Differential Encode Mode Enabled 10 mW (No increase for Nap or Sleep Modes)
TIMING CHARACTERISTICS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fS Sampling Frequency (Note 10) l 1 150 MHz tL ENC Low Time (Note 8) Duty Cycle Stabilizer Off l 3.17 3.33 500 ns Duty Cycle Stabilizer On l 2.0 3.33 500 ns tH ENC High Time (Note 8) Duty Cycle Stabilizer Off l 3.17 3.33 500 ns Duty Cycle Stabilizer On l 2.0 3.33 500 ns tAP Sample-and-Hold Acquisition Delay 0 ns Time
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Digital Data Outputs (CMOS Modes: Full Data Rate and Double Data Rate)
tD ENC to Data Delay CL = 5pF (Note 8) l 1.1 1.7 3.1 ns tC ENC to CLKOUT Delay CL = 5pF (Note 8) l 1 1.4 2.6 ns tSKEW DATA to CLKOUT Skew tD – tC (Note 8) l 0 0.3 0.6 ns Pipeline Latency Full Data Rate Mode 5.0 Cycles Double Data Rate Mode 5.5 Cycles
Digital Data Outputs (LVDS Mode)
tD ENC to Data Delay CL = 5pF (Note 8) l 1.1 1.8 3.2 ns tC ENC to CLKOUT Delay CL = 5pF (Note 8) l 1 1.5 2.7 ns tSKEW DATA to CLKOUT Skew tD – tC (Note 8) l 0 0.3 0.6 ns Pipeline Latency 5.5 Cycles 226214fc 6 For more information www.linear.com/LTC2262-14 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configurations Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Outputs Power Requirements Timing Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Functional Block Diagram Applications Information Typical Applications Package Description Revision History Related Parts
POWER REQUIREMENTS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 9) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS LVDS Output Mode
VDD Analog Supply Voltage (Note 10) l 1.7 1.8 1.9 V OVDD Output Supply Voltage (Note 10) l 1.7 1.9 V IVDD Analog Supply Current Sine Wave Input l 88.1 101.3 mA IOVDD Digital Supply Current Sine Input, 1.75mA Mode l 20.7 23 mA (0VDD = 1.8V) Sine Input, 3.5mA Mode l 40.5 44 mA PDISS Power Dissipation Sine Input, 1.75mA Mode l 196 224 mW Sine Input, 3.5mA Mode l 231 262 mW
All Output Modes
PSLEEP Sleep Mode Power 0.5 mW PNAP Nap Mode Power 9 mW PDIFFCLK Power Increase with Differential Encode Mode Enabled 10 mW (No increase for Nap or Sleep Modes)
TIMING CHARACTERISTICS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fS Sampling Frequency (Note 10) l 1 150 MHz tL ENC Low Time (Note 8) Duty Cycle Stabilizer Off l 3.17 3.33 500 ns Duty Cycle Stabilizer On l 2.0 3.33 500 ns tH ENC High Time (Note 8) Duty Cycle Stabilizer Off l 3.17 3.33 500 ns Duty Cycle Stabilizer On l 2.0 3.33 500 ns tAP Sample-and-Hold Acquisition Delay 0 ns Time
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Digital Data Outputs (CMOS Modes: Full Data Rate and Double Data Rate)
tD ENC to Data Delay CL = 5pF (Note 8) l 1.1 1.7 3.1 ns tC ENC to CLKOUT Delay CL = 5pF (Note 8) l 1 1.4 2.6 ns tSKEW DATA to CLKOUT Skew tD – tC (Note 8) l 0 0.3 0.6 ns Pipeline Latency Full Data Rate Mode 5.0 Cycles Double Data Rate Mode 5.5 Cycles
Digital Data Outputs (LVDS Mode)
tD ENC to Data Delay CL = 5pF (Note 8) l 1.1 1.8 3.2 ns tC ENC to CLKOUT Delay CL = 5pF (Note 8) l 1 1.5 2.7 ns tSKEW DATA to CLKOUT Skew tD – tC (Note 8) l 0 0.3 0.6 ns Pipeline Latency 5.5 Cycles 226214fc 6 For more information www.linear.com/LTC2262-14 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configurations Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Outputs Power Requirements Timing Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Functional Block Diagram Applications Information Typical Applications Package Description Revision History Related Parts