Datasheet LTC2261-12, LTC2260-12, LTC2259-12 (Analog Devices) - 7

LTC2261-12 LTC2260-12/LTC2259-12
T iMing characTerisTics The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Digital Data Outputs (LVDS Mode)
tD ENC to Data Delay CL = 5pF (Note 8) l 1.1 1.8 3.2 ns tC ENC to CLKOUT Delay CL = 5pF (Note 8) l 1 1.5 2.7 ns tSKEW DATA to CLKOUT Skew tD – tC (Note 8) l 0 0.3 0.6 ns Pipeline Latency 5.5 Cycles
SPI Port Timing (Note 8)
tSCK SCK Period Write Mode l 40 ns Readback Mode, CSDO = 20pF, RPULLUP = 2k l 250 ns tS CS to SCK Setup Time l 5 ns tH SCK to CS Setup Time l 5 ns tDS SDI Setup Time l 5 ns tDH SDI Hold Time l 5 ns tDO SCK Falling to SDO Valid Readback Mode, CSDO = 20pF, RPULLUP = 2k l 125 ns
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings termination disabled, differential ENC+/ENC– = 2VP-P sine wave, input may cause permanent damage to the device. Exposure to any Absolute range = 2VP-P with differential drive, unless otherwise noted. Maximum Rating condition for extended periods may affect device
Note 6:
Integral nonlinearity is defined as the deviation of a code from a reliability and lifetime. best fit straight line to the transfer curve. The deviation is measured from
Note 2:
All voltage values are with respect to GND with GND and OGND the center of the quantization band. shorted (unless otherwise noted).
Note 7:
Offset error is the offset voltage measured from –0.5 LSB when
Note 3:
When these pin voltages are taken below GND or above VDD, they the output code flickers between 0000 0000 0000 and 1111 1111 1111 in will be clamped by internal diodes. This product can handle input currents 2’s complement output mode. of greater than 100mA below GND or above VDD without latchup.
Note 8:
Guaranteed by design, not subject to test.
Note 4:
When these pin voltages are taken below GND they will be
Note 9:
VDD = 1.8V, fSAMPLE = 125MHz (LTC2261), 105MHz (LTC2260), clamped by internal diodes. When these pin voltages are taken above VDD or 80MHz (LTC2259), ENC+ = single-ended 1.8V square wave, ENC– = 0V, they will not be clamped by internal diodes. This product can handle input input range = 2VP-P with differential drive, 5pF load on each digital output currents of greater than 100mA below GND without latchup. unless otherwise noted.
Note 5:
VDD = OVDD = 1.8V, fSAMPLE = 125MHz (LTC2261),
Note 10:
Recommended operating conditions. 105MHz (LTC2260), or 80MHz (LTC2259), LVDS outputs with internal
TiMing DiagraMs Full-Rate CMOS Output Mode Timing All Outputs Are Single Ended and Have CMOS Levels
tAP ANALOG N N + 2 N + 4 INPUT N + 3 tH N + 1 tL ENC– ENC+ tD D0-D11, OF N – 5 N – 4 N – 3 N – 2 N – 1 tC CLKOUT+ CLKOUT– 226112 TD01 226112fc For more information www.linear.com/LTC2261-12 7 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configurations Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Outputs Power Requirements Timing Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Functional Block Diagram Applications Information Typical Applications Package Description Revision History Related Parts