Datasheet LTC2255, LTC2254 (Analog Devices) - 10
| Hersteller | Analog Devices |
| Beschreibung | 14-Bit, 125Msps Low Power 3V ADCs |
| Seiten / Seite | 24 / 10 — PI FU CTIO S. AIN+ (Pin 1):. D0 – D13 (Pins 12, 13, 14, 15, 16, 17, 18, … |
| Dateiformat / Größe | PDF / 640 Kb |
| Dokumentensprache | Englisch |
PI FU CTIO S. AIN+ (Pin 1):. D0 – D13 (Pins 12, 13, 14, 15, 16, 17, 18, 19, 22, 23, 24, 25, 26, 27):. AIN- (Pin 2):
Modelllinie für dieses Datenblatt
Textversion des Dokuments
LTC2255/LTC2254
U U U PI FU CTIO S AIN+ (Pin 1):
Positive Differential Analog Input.
D0 – D13 (Pins 12, 13, 14, 15, 16, 17, 18, 19, 22, 23, 24, 25, 26, 27):
Digital Outputs. D13 is the MSB.
AIN- (Pin 2):
Negative Differential Analog Input.
OGND (Pin 20):
Output Driver Ground.
REFH (Pins 3, 4):
ADC High Reference. Short together and bypass to pins 5, 6 with a 0.1µF ceramic chip capacitor as
OVDD (Pin 21):
Positive Supply for the Output Drivers. close to the pin as possible. Also bypass to pins 5, 6 with Bypass to ground with 0.1µF ceramic chip capacitor. OVDD an additional 2.2µF ceramic chip capacitor and to ground can be 0.5V to 3.6V. with a 1µF ceramic chip capacitor.
OF (Pin 28):
Over/Under Flow Output. High when an over
REFL (Pins 5, 6):
ADC Low Reference. Short together and or under flow has occurred. bypass to pins 3, 4 with a 0.1µF ceramic chip capacitor as
MODE (Pin 29):
Output Format and Clock Duty Cycle close to the pin as possible. Also bypass to pins 3, 4 with Stabilizer Selection Pin. Connecting MODE to GND selects an additional 2.2µF ceramic chip capacitor and to ground offset binary output format and turns the clock duty cycle with a 1µF ceramic chip capacitor. stabilizer off. 1/3 VDD selects offset binary output format
VDD (Pins 7, 32):
3V Supply. Bypass to GND with 0.1µF and turns the clock duty cycle stabilizer on. 2/3 VDD selects ceramic chip capacitors. 2’s complement output format and turns the clock duty cycle stabilizer on. V
GND (Pin 8):
ADC Power Ground. DD selects 2’s complement output format and turns the clock duty cycle stabilizer off.
CLK (Pin 9):
Clock Input. The input sample starts on the
SENSE (Pin 30):
Reference Programming Pin. Connecting positive edge. SENSE to VCM selects the internal reference and a ±0.5V
SHDN (Pin 10):
Shutdown Mode Selection Pin. Connect- input range. VDD selects the internal reference and a ±1V ing SHDN to GND and OE to GND results in normal input range. An external reference greater than 0.5V and operation with the outputs enabled. Connecting SHDN to less than 1V applied to SENSE selects an input range of GND and OE to VDD results in normal operation with the ±VSENSE. ±1V is the largest valid input range. outputs at high impedance. Connecting SHDN to VDD and
V
OE to GND results in nap mode with the outputs at high
CM (Pin 31):
1.5V Output and Input Common Mode Bias. Bypass to ground with 2.2µF ceramic chip capacitor. impedance. Connecting SHDN to VDD and OE to VDD results in sleep mode with the outputs at high impedance.
GND (Exposed Pad) (Pin 33):
ADC Power Ground. The exposed pad on the bottom of the package needs to be
OE (Pin 11):
Output Enable Pin. Refer to SHDN pin soldered to ground. function. 22554fa 10
U U U PI FU CTIO S AIN+ (Pin 1):
Positive Differential Analog Input.
D0 – D13 (Pins 12, 13, 14, 15, 16, 17, 18, 19, 22, 23, 24, 25, 26, 27):
Digital Outputs. D13 is the MSB.
AIN- (Pin 2):
Negative Differential Analog Input.
OGND (Pin 20):
Output Driver Ground.
REFH (Pins 3, 4):
ADC High Reference. Short together and bypass to pins 5, 6 with a 0.1µF ceramic chip capacitor as
OVDD (Pin 21):
Positive Supply for the Output Drivers. close to the pin as possible. Also bypass to pins 5, 6 with Bypass to ground with 0.1µF ceramic chip capacitor. OVDD an additional 2.2µF ceramic chip capacitor and to ground can be 0.5V to 3.6V. with a 1µF ceramic chip capacitor.
OF (Pin 28):
Over/Under Flow Output. High when an over
REFL (Pins 5, 6):
ADC Low Reference. Short together and or under flow has occurred. bypass to pins 3, 4 with a 0.1µF ceramic chip capacitor as
MODE (Pin 29):
Output Format and Clock Duty Cycle close to the pin as possible. Also bypass to pins 3, 4 with Stabilizer Selection Pin. Connecting MODE to GND selects an additional 2.2µF ceramic chip capacitor and to ground offset binary output format and turns the clock duty cycle with a 1µF ceramic chip capacitor. stabilizer off. 1/3 VDD selects offset binary output format
VDD (Pins 7, 32):
3V Supply. Bypass to GND with 0.1µF and turns the clock duty cycle stabilizer on. 2/3 VDD selects ceramic chip capacitors. 2’s complement output format and turns the clock duty cycle stabilizer on. V
GND (Pin 8):
ADC Power Ground. DD selects 2’s complement output format and turns the clock duty cycle stabilizer off.
CLK (Pin 9):
Clock Input. The input sample starts on the
SENSE (Pin 30):
Reference Programming Pin. Connecting positive edge. SENSE to VCM selects the internal reference and a ±0.5V
SHDN (Pin 10):
Shutdown Mode Selection Pin. Connect- input range. VDD selects the internal reference and a ±1V ing SHDN to GND and OE to GND results in normal input range. An external reference greater than 0.5V and operation with the outputs enabled. Connecting SHDN to less than 1V applied to SENSE selects an input range of GND and OE to VDD results in normal operation with the ±VSENSE. ±1V is the largest valid input range. outputs at high impedance. Connecting SHDN to VDD and
V
OE to GND results in nap mode with the outputs at high
CM (Pin 31):
1.5V Output and Input Common Mode Bias. Bypass to ground with 2.2µF ceramic chip capacitor. impedance. Connecting SHDN to VDD and OE to VDD results in sleep mode with the outputs at high impedance.
GND (Exposed Pad) (Pin 33):
ADC Power Ground. The exposed pad on the bottom of the package needs to be
OE (Pin 11):
Output Enable Pin. Refer to SHDN pin soldered to ground. function. 22554fa 10