Datasheet LTC2241-12 (Analog Devices) - 5
| Hersteller | Analog Devices |
| Beschreibung | 12-Bit, 210Msps ADC |
| Seiten / Seite | 30 / 5 — power requireMenTs The. denotes the specifications which apply over the … |
| Dateiformat / Größe | PDF / 753 Kb |
| Dokumentensprache | Englisch |
power requireMenTs The. denotes the specifications which apply over the full operating temperature
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Textversion des Dokuments
LTC2241-12
power requireMenTs The
●
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 9) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V DD Analog Supply Voltage (Note 8) ● 2.375 2.5 2.625 V PSLEEP Sleep Mode Power SHDN = High, OE = High, No CLK 1 mW PNAP Nap Mode Power SHDN = High, OE = Low, No CLK 28 mW
LVDS OUTPUT MODE
OVDD Output Supply Voltage (Note 8) ● 2.375 2.5 2.625 V IVDD Analog Supply Current ● 226 252 mA IOVDD Output Supply Current ● 58 70 mA PDISS Power Dissipation ● 710 805 mW
CMOS OUTPUT MODE
OVDD Output Supply Voltage (Note 8) ● 0.5 2.5 2.625 V IVDD Analog Supply Current (Note 7) ● 226 252 mA PDISS Power Dissipation 585 mW
TiMing characTerisTics The
●
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fS Sampling Frequency (Note 8) ● 1 210 MHz tL ENC Low Time (Note 7) Duty Cycle Stabilizer Off ● 2.26 2.38 500 ns Duty Cycle Stabilizer On ● 1.5 2.38 500 ns tH ENC High Time (Note 7) Duty Cycle Stabilizer Off ● 2.26 2.38 500 ns Duty Cycle Stabilizer On ● 1.5 2.38 500 ns tAP Sample-and-Hold Aperture Delay 0.4 ns tOE Output Enable Delay (Note 7) ● 5 10 ns
LVDS OUTPUT MODE
tD ENC to DATA Delay (Note 7) ● 1 1.7 2.8 ns tC ENC to CLKOUT Delay (Note 7) ● 1 1.7 2.8 ns DATA to CLKOUT Skew (tC – tD) (Note 7) ● –0.6 0 0.6 ns Rise Time 0.5 ns Fall Time 0.5 ns Pipeline Latency 5 Cycles
CMOS OUTPUT MODE
tD ENC to DATA Delay (Note 7) ● 1 1.7 2.8 ns tC ENC to CLKOUT Delay (Note 7) ● 1 1.7 2.8 ns DATA to CLKOUT Skew (tC – tD) (Note 7) ● –0.6 0 0.6 ns Pipeline Full Rate CMOS 5 Cycles Latency Demuxed Interleaved 5 Cycles Demuxed Simultaneous 5 and 6 Cycles 224112fc 5 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Digital Outputs Power Requirements Timing Characteristics Electrical Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagrams Applications Information Package Description Revision History Related Parts
power requireMenTs The
●
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 9) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V DD Analog Supply Voltage (Note 8) ● 2.375 2.5 2.625 V PSLEEP Sleep Mode Power SHDN = High, OE = High, No CLK 1 mW PNAP Nap Mode Power SHDN = High, OE = Low, No CLK 28 mW
LVDS OUTPUT MODE
OVDD Output Supply Voltage (Note 8) ● 2.375 2.5 2.625 V IVDD Analog Supply Current ● 226 252 mA IOVDD Output Supply Current ● 58 70 mA PDISS Power Dissipation ● 710 805 mW
CMOS OUTPUT MODE
OVDD Output Supply Voltage (Note 8) ● 0.5 2.5 2.625 V IVDD Analog Supply Current (Note 7) ● 226 252 mA PDISS Power Dissipation 585 mW
TiMing characTerisTics The
●
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fS Sampling Frequency (Note 8) ● 1 210 MHz tL ENC Low Time (Note 7) Duty Cycle Stabilizer Off ● 2.26 2.38 500 ns Duty Cycle Stabilizer On ● 1.5 2.38 500 ns tH ENC High Time (Note 7) Duty Cycle Stabilizer Off ● 2.26 2.38 500 ns Duty Cycle Stabilizer On ● 1.5 2.38 500 ns tAP Sample-and-Hold Aperture Delay 0.4 ns tOE Output Enable Delay (Note 7) ● 5 10 ns
LVDS OUTPUT MODE
tD ENC to DATA Delay (Note 7) ● 1 1.7 2.8 ns tC ENC to CLKOUT Delay (Note 7) ● 1 1.7 2.8 ns DATA to CLKOUT Skew (tC – tD) (Note 7) ● –0.6 0 0.6 ns Rise Time 0.5 ns Fall Time 0.5 ns Pipeline Latency 5 Cycles
CMOS OUTPUT MODE
tD ENC to DATA Delay (Note 7) ● 1 1.7 2.8 ns tC ENC to CLKOUT Delay (Note 7) ● 1 1.7 2.8 ns DATA to CLKOUT Skew (tC – tD) (Note 7) ● –0.6 0 0.6 ns Pipeline Full Rate CMOS 5 Cycles Latency Demuxed Interleaved 5 Cycles Demuxed Simultaneous 5 and 6 Cycles 224112fc 5 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Digital Outputs Power Requirements Timing Characteristics Electrical Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagrams Applications Information Package Description Revision History Related Parts