Datasheet LTC2240-12 (Analog Devices) - 5
| Hersteller | Analog Devices |
| Beschreibung | 12-Bit, 170Msps ADC |
| Seiten / Seite | 30 / 5 — DIGITAL INPUTS AND DIGITAL OUTPUTS The. denotes the specifi cations which … |
| Dateiformat / Größe | PDF / 555 Kb |
| Dokumentensprache | Englisch |
DIGITAL INPUTS AND DIGITAL OUTPUTS The. denotes the specifi cations which apply over the
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LTC2240-12
DIGITAL INPUTS AND DIGITAL OUTPUTS The
l
denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS LOGIC OUTPUTS (LVDS MODE)
VOD Differential Output Voltage 100Ω Differential Load l 247 350 454 mV VOS Output Common Mode Voltage 100Ω Differential Load l 1.125 1.250 1.375 V
POWER REQUIREMENTS The
l
denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 9) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V DD Analog Supply Voltage (Note 8) l 2.375 2.5 2.625 V PSLEEP Sleep Mode Power SHDN = High, OE = High, No CLK 1 mW PNAP Nap Mode Power SHDN = High, OE = Low, No CLK 28 mW
LVDS OUTPUT MOD
OVDD Output Supply Voltage (Note 8) l 2.375 2.5 2.625 V IVDD Analog Supply Current l 170 185 mA IOVDD Output Supply Current l 58 70 mA PDISS Power Dissipation l 570 638 mW
CMOS OUTPUT MODE
OVDD Output Supply Voltage (Note 8) l 0.5 2.5 2.625 V IVDD Analog Supply Current (Note 7) l 170 185 mA PDISS Power Dissipation 445 mW
TIMING CHARACTERISTICS The
l
denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fS Sampling Frequency (Note 8) l 1 170 MHz tL ENC Low Time (Note 7) Duty Cycle Stabilizer Off l 2.79 2.94 500 ns Duty Cycle Stabilizer On l 1.5 2.94 500 ns tH ENC High Time (Note 7) Duty Cycle Stabilizer Off l 2.79 2.94 500 ns Duty Cycle Stabilizer On l 1.5 2.94 500 ns tAP Sample-and-Hold Aperture Delay 0.4 ns tOE Output Enable Delay (Note 7) l 5 10 ns
LVDS OUTPUT MODE
tD ENC to DATA Delay (Note 7) l 1 1.7 2.8 ns tC ENC to CLKOUT Delay (Note 7) l 1 1.7 2.8 ns DATA to CLKOUT Skew (tC – tD) (Note 7) l –0.6 0 0.6 ns Rise Time 0.5 ns Fall Time 0.5 ns Pipeline Latency 5 Cycles
CMOS OUTPUT MODE
tD ENC to DATA Delay (Note 7) l 1 1.7 2.8 ns tC ENC to CLKOUT Delay (Note 7) l 1 1.7 2.8 ns 224012fd 5 Document Outline FEATURES DESCRIPTION APPLICATIONS TYPICAL APPLICATION ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION ORDER INFORMATION CONVERTER CHARACTERISTICS ANALOG INPUT DYNAMIC ACCURACY INTERNAL REFERENCE CHARACTERISTICS DIGITAL INPUTS AND DIGITAL OUTPUTS POWER REQUIREMENTS TIMING CHARACTERISTICS ELECTRICAL CHARACTERISTICS TYPICAL PERFORMANCE CHARACTERISTICS PIN FUNCTIONS FUNCTIONAL BLOCK DIAGRAM TIMING DIAGRAMS APPLICATIONS INFORMATION PACKAGE DESCRIPTION REVISION HISTORY RELATED PARTS
DIGITAL INPUTS AND DIGITAL OUTPUTS The
l
denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS LOGIC OUTPUTS (LVDS MODE)
VOD Differential Output Voltage 100Ω Differential Load l 247 350 454 mV VOS Output Common Mode Voltage 100Ω Differential Load l 1.125 1.250 1.375 V
POWER REQUIREMENTS The
l
denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 9) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V DD Analog Supply Voltage (Note 8) l 2.375 2.5 2.625 V PSLEEP Sleep Mode Power SHDN = High, OE = High, No CLK 1 mW PNAP Nap Mode Power SHDN = High, OE = Low, No CLK 28 mW
LVDS OUTPUT MOD
OVDD Output Supply Voltage (Note 8) l 2.375 2.5 2.625 V IVDD Analog Supply Current l 170 185 mA IOVDD Output Supply Current l 58 70 mA PDISS Power Dissipation l 570 638 mW
CMOS OUTPUT MODE
OVDD Output Supply Voltage (Note 8) l 0.5 2.5 2.625 V IVDD Analog Supply Current (Note 7) l 170 185 mA PDISS Power Dissipation 445 mW
TIMING CHARACTERISTICS The
l
denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fS Sampling Frequency (Note 8) l 1 170 MHz tL ENC Low Time (Note 7) Duty Cycle Stabilizer Off l 2.79 2.94 500 ns Duty Cycle Stabilizer On l 1.5 2.94 500 ns tH ENC High Time (Note 7) Duty Cycle Stabilizer Off l 2.79 2.94 500 ns Duty Cycle Stabilizer On l 1.5 2.94 500 ns tAP Sample-and-Hold Aperture Delay 0.4 ns tOE Output Enable Delay (Note 7) l 5 10 ns
LVDS OUTPUT MODE
tD ENC to DATA Delay (Note 7) l 1 1.7 2.8 ns tC ENC to CLKOUT Delay (Note 7) l 1 1.7 2.8 ns DATA to CLKOUT Skew (tC – tD) (Note 7) l –0.6 0 0.6 ns Rise Time 0.5 ns Fall Time 0.5 ns Pipeline Latency 5 Cycles
CMOS OUTPUT MODE
tD ENC to DATA Delay (Note 7) l 1 1.7 2.8 ns tC ENC to CLKOUT Delay (Note 7) l 1 1.7 2.8 ns 224012fd 5 Document Outline FEATURES DESCRIPTION APPLICATIONS TYPICAL APPLICATION ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION ORDER INFORMATION CONVERTER CHARACTERISTICS ANALOG INPUT DYNAMIC ACCURACY INTERNAL REFERENCE CHARACTERISTICS DIGITAL INPUTS AND DIGITAL OUTPUTS POWER REQUIREMENTS TIMING CHARACTERISTICS ELECTRICAL CHARACTERISTICS TYPICAL PERFORMANCE CHARACTERISTICS PIN FUNCTIONS FUNCTIONAL BLOCK DIAGRAM TIMING DIAGRAMS APPLICATIONS INFORMATION PACKAGE DESCRIPTION REVISION HISTORY RELATED PARTS