Datasheet LTC2234 (Analog Devices)
| Hersteller | Analog Devices |
| Beschreibung | 10-Bit, 135Msps ADC |
| Seiten / Seite | 24 / 1 — FEATURES. DESCRIPTIO. Sample Rate: 135Msps. 61dB SNR up to 200MHz Input. … |
| Dateiformat / Größe | PDF / 620 Kb |
| Dokumentensprache | Englisch |
FEATURES. DESCRIPTIO. Sample Rate: 135Msps. 61dB SNR up to 200MHz Input. 75dB SFDR up to 400MHz Input
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LTC2234 10-Bit, 135Msps ADC
U FEATURES DESCRIPTIO
■
Sample Rate: 135Msps
The LTC®2234 is a 135Msps, sampling 10-bit A/D con- ■
61dB SNR up to 200MHz Input
verter designed for digitizing high frequency, wide dy- ■
75dB SFDR up to 400MHz Input
namic range signals. The LTC2234 is perfect for demand- ■
775MHz Full Power Bandwidth S/H
ing communications applications with AC performance ■
Single 3.3V Supply
that includes 60.5dB SNR and 75dB spurious free dy- ■
Low Power Dissipation: 630mW
namic range for signals up to 400MHz. Ultralow jitter of ■ CMOS Outputs 0.15psRMS allows undersampling of IF frequencies with ■ Selectable Input Ranges: ±0.5V or ±1V excellent noise performance. ■ No Missing Codes DC specs include ±0.2LSB INL (typ), ±0.1LSB DNL (typ) ■ Optional Clock Duty Cycle Stabilizer and ±0.8LSB INL, ±0.6LSB DNL over temperature. The ■ Shutdown and Nap Modes transition noise is a low 0.12LSB ■ Data Ready Output Clock RMS. ■ Pin Compatible Family A separate output power supply allows the CMOS output 135Msps: LTC2224 (12-Bit), LTC2234 (10-Bit) swing to range from 0.5V to 3.6V. 105Msps: LTC2222 (12-Bit), LTC2232 (10-Bit) The ENC+ and ENC– inputs may be driven differentially or 80Msps: LTC2223 (12-Bit), LTC2233 (10-Bit) single ended with a sine wave, PECL, LVDS, TTL, or CMOS ■ 48-Pin 7mm × 7mm QFN Package inputs. An optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty
U
cycles.
APPLICATIO S
■ Wireless and Wired Broadband Communication , LTC and LT are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. ■ Cable Head-End Systems ■ Power Amplifier Linearization ■ Communications Test Equipment
U TYPICAL APPLICATIO
3.3V
SFDR vs Input Frequency
VDD 90 REFH FLEXIBLE 85 0.5V TO 3.6V 4th OR HIGHER REFL REFERENCE OVDD 80 75 2nd OR 3rd + D9 10-BIT • 70 ANALOG INPUT CORRECTION OUTPUT PIPELINED • INPUT S/H LOGIC DRIVERS ADC CORE • SFDR (dBFS) 65 – D0 60 OGND 55 CLOCK/DUTY 50 CYCLE 0 100 200 300 400 500 600 CONTROL INPUT FREQUENCY (MHz) 2234 TA01b 2234 TA01 ENCODE INPUT 2234fa 1
U FEATURES DESCRIPTIO
■
Sample Rate: 135Msps
The LTC®2234 is a 135Msps, sampling 10-bit A/D con- ■
61dB SNR up to 200MHz Input
verter designed for digitizing high frequency, wide dy- ■
75dB SFDR up to 400MHz Input
namic range signals. The LTC2234 is perfect for demand- ■
775MHz Full Power Bandwidth S/H
ing communications applications with AC performance ■
Single 3.3V Supply
that includes 60.5dB SNR and 75dB spurious free dy- ■
Low Power Dissipation: 630mW
namic range for signals up to 400MHz. Ultralow jitter of ■ CMOS Outputs 0.15psRMS allows undersampling of IF frequencies with ■ Selectable Input Ranges: ±0.5V or ±1V excellent noise performance. ■ No Missing Codes DC specs include ±0.2LSB INL (typ), ±0.1LSB DNL (typ) ■ Optional Clock Duty Cycle Stabilizer and ±0.8LSB INL, ±0.6LSB DNL over temperature. The ■ Shutdown and Nap Modes transition noise is a low 0.12LSB ■ Data Ready Output Clock RMS. ■ Pin Compatible Family A separate output power supply allows the CMOS output 135Msps: LTC2224 (12-Bit), LTC2234 (10-Bit) swing to range from 0.5V to 3.6V. 105Msps: LTC2222 (12-Bit), LTC2232 (10-Bit) The ENC+ and ENC– inputs may be driven differentially or 80Msps: LTC2223 (12-Bit), LTC2233 (10-Bit) single ended with a sine wave, PECL, LVDS, TTL, or CMOS ■ 48-Pin 7mm × 7mm QFN Package inputs. An optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty
U
cycles.
APPLICATIO S
■ Wireless and Wired Broadband Communication , LTC and LT are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. ■ Cable Head-End Systems ■ Power Amplifier Linearization ■ Communications Test Equipment
U TYPICAL APPLICATIO
3.3V
SFDR vs Input Frequency
VDD 90 REFH FLEXIBLE 85 0.5V TO 3.6V 4th OR HIGHER REFL REFERENCE OVDD 80 75 2nd OR 3rd + D9 10-BIT • 70 ANALOG INPUT CORRECTION OUTPUT PIPELINED • INPUT S/H LOGIC DRIVERS ADC CORE • SFDR (dBFS) 65 – D0 60 OGND 55 CLOCK/DUTY 50 CYCLE 0 100 200 300 400 500 600 CONTROL INPUT FREQUENCY (MHz) 2234 TA01b 2234 TA01 ENCODE INPUT 2234fa 1