Datasheet LTC2226H (Analog Devices) - 10

LTC2226H
APPLICATIONS INFORMATION
DAC to produce a residue. The residue is amplified and LTC2226H output by the residue amplifier. Successive stages operate VDD out of phase so that when the odd stages are outputting CSAMPLE 4pF their residue, the even stages are acquiring that residue 15Ω AIN+ and vice versa. CPARASITIC 1pF VDD When CLK is low, the analog input is sampled differentially CSAMPLE 4pF directly onto the input sample-and-hold capacitors, inside 15Ω AIN– the “Input S/H” shown in the block diagram. At the instant CPARASITIC 1pF that CLK transitions from low to high, the sampled input is held. While CLK is high, the held input voltage is buffered CLK by the S/H amplifier which drives the first pipelined ADC stage. The first stage acquires the output of the S/H dur- 2226H F02 ing this high phase of CLK. When CLK goes back low, the first stage produces its residue which is acquired by the
Figure 2. Equivalent Input Circuit
second stage. At the same time, the input S/H goes back to acquiring the analog input. When CLK goes back high, the the inputs are reconnected to the sampling capacitors to second stage produces its residue which is acquired by the acquire a new sample. Since the sampling capacitors still third stage. An identical process is repeated for the third, hold the previous sample, a charging glitch proportional fourth and fifth stages, resulting in a fifth stage residue to the change in voltage between samples will be seen that is sent to the sixth stage ADC for final evaluation. at this time. If the change between the last sample and the new sample is small, the charging glitch seen at the Each ADC stage following the first has additional range to input will be small. If the input change is large, such as accommodate flash and amplifier offset errors. Results the change seen with input frequencies near Nyquist, then from all of the ADC stages are digitally synchronized such a larger charging glitch will be seen. that the results can be properly combined in the correction logic before being sent to the output buffer.
Single-Ended Input
For cost sensitive applications, the analog inputs can be
SAMPLE/HOLD OPERATION AND INPUT DRIVE
driven single-ended. With a single-ended input the har-
Sample/Hold Operation
monic distortion and INL will degrade, but the SNR and DNL will remain unchanged. For a single-ended input, A + IN Figure 2 shows an equivalent circuit for the LTC2226H should be driven with the input signal and A – IN should CMOS differential sample-and-hold. The analog inputs are be connected to VCM or a low noise reference voltage connected to the sampling capacitors (CSAMPLE) through between 1V and 1.5V. NMOS transistors. The capacitors shown attached to each input (CPARASITIC) are the summation of all other
Common Mode Bias
capacitance associated with each input. For optimal performance the analog inputs should be driven During the sample phase when CLK is low, the transistors differentially. Each input should swing ±0.5V for the 2V connect the analog inputs to the sampling capacitors and range or ±0.25V for the 1V range, around a common mode they charge to and track the differential input voltage. When voltage of 1.5V. The VCM output pin (Pins 44, 45) may be CLK transitions from low to high, the sampled input voltage used to provide the common mode bias level. VCM can be is held on the sampling capacitors. During the hold phase tied directly to the center tap of a transformer to set the DC when CLK is high, the sampling capacitors are disconnected input level or as a reference level to an op amp differential from the input and the held voltage is passed to the ADC driver circuit. The VCM pins must be bypassed to ground core for processing. As CLK transitions from high to low, close to the ADC with a 2.2µF or greater capacitor. 2226hfc 10