Datasheet LTC2224 (Analog Devices)
| Hersteller | Analog Devices |
| Beschreibung | 12-Bit, 135Msps ADC |
| Seiten / Seite | 24 / 1 — FEATURES. DESCRIPTIO. Sample Rate: 135Msps. 67.3dB SNR up to 140MHz … |
| Dateiformat / Größe | PDF / 625 Kb |
| Dokumentensprache | Englisch |
FEATURES. DESCRIPTIO. Sample Rate: 135Msps. 67.3dB SNR up to 140MHz Input. 80dB SFDR up to 150MHz Input
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LTC2224 12-Bit, 135Msps ADC
U FEATURES DESCRIPTIO
■
Sample Rate: 135Msps
The LTC®2224 is a 135Msps, sampling 12-bit A/D con- ■
67.3dB SNR up to 140MHz Input
verter designed for digitizing high frequency, wide dy- ■
80dB SFDR up to 150MHz Input
namic range signals. The LTC2224 is perfect for demand- ■
775MHz Full Power Bandwidth S/H
ing communications applications with AC performance ■
Single 3.3V Supply
that includes 67.3dB SNR and 80dB spurious free dy- ■
Low Power Dissipation: 630mW
namic range for signals up to 150MHz. Ultralow jitter of ■ CMOS Outputs 0.15psRMS allows undersampling of IF frequencies with ■ Selectable Input Ranges: ±0.5V or ±1V excellent noise performance. ■ No Missing Codes DC specs include ±0.4LSB INL (typ), ±0.3LSB DNL (typ) ■ Optional Clock Duty Cycle Stabilizer and no missing codes over temperature. The transition ■ Shutdown and Nap Modes noise is a low 0.5LSB ■ Data Ready Output Clock RMS. ■ Pin Compatible Family A separate output power supply allows the CMOS output 135Msps: LTC2224 (12-Bit), LTC2234 (10-Bit) swing to range from 0.5V to 3.6V. 105Msps: LTC2222 (12-Bit), LTC2232 (10-Bit) The ENC+ and ENC– inputs may be driven differentially or 80Msps: LTC2223 (12-Bit), LTC2233 (10-Bit) single ended with a sine wave, PECL, LVDS, TTL, or CMOS ■ 48-Pin 7mm × 7mm QFN Package inputs. An optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty
U APPLICATIO S
cycles. ■ Wireless and Wired Broadband Communication , LTC and LT are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. ■ Cable Head-End Systems ■ Power Amplifier Linearization ■ Communications Test Equipment
U TYPICAL APPLICATIO
3.3V
SFDR vs Input Frequency
VDD 95 REFH FLEXIBLE 0.5V TO 3.6V 90 REFL REFERENCE 4th OR HIGHER OVDD 85 80 + D11 75 12-BIT • ANALOG INPUT CORRECTION OUTPUT 2nd OR 3rd PIPELINED • INPUT 70 S/H LOGIC DRIVERS ADC CORE • SFDR (dBFS) – D0 65 60 OGND 55 CLOCK/DUTY CYCLE 50 0 100 200 300 400 500 600 CONTROL INPUT FREQUENCY (MHz) 2224 TA01 2224 TA01b ENCODE INPUT 2224fa 1
U FEATURES DESCRIPTIO
■
Sample Rate: 135Msps
The LTC®2224 is a 135Msps, sampling 12-bit A/D con- ■
67.3dB SNR up to 140MHz Input
verter designed for digitizing high frequency, wide dy- ■
80dB SFDR up to 150MHz Input
namic range signals. The LTC2224 is perfect for demand- ■
775MHz Full Power Bandwidth S/H
ing communications applications with AC performance ■
Single 3.3V Supply
that includes 67.3dB SNR and 80dB spurious free dy- ■
Low Power Dissipation: 630mW
namic range for signals up to 150MHz. Ultralow jitter of ■ CMOS Outputs 0.15psRMS allows undersampling of IF frequencies with ■ Selectable Input Ranges: ±0.5V or ±1V excellent noise performance. ■ No Missing Codes DC specs include ±0.4LSB INL (typ), ±0.3LSB DNL (typ) ■ Optional Clock Duty Cycle Stabilizer and no missing codes over temperature. The transition ■ Shutdown and Nap Modes noise is a low 0.5LSB ■ Data Ready Output Clock RMS. ■ Pin Compatible Family A separate output power supply allows the CMOS output 135Msps: LTC2224 (12-Bit), LTC2234 (10-Bit) swing to range from 0.5V to 3.6V. 105Msps: LTC2222 (12-Bit), LTC2232 (10-Bit) The ENC+ and ENC– inputs may be driven differentially or 80Msps: LTC2223 (12-Bit), LTC2233 (10-Bit) single ended with a sine wave, PECL, LVDS, TTL, or CMOS ■ 48-Pin 7mm × 7mm QFN Package inputs. An optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty
U APPLICATIO S
cycles. ■ Wireless and Wired Broadband Communication , LTC and LT are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. ■ Cable Head-End Systems ■ Power Amplifier Linearization ■ Communications Test Equipment
U TYPICAL APPLICATIO
3.3V
SFDR vs Input Frequency
VDD 95 REFH FLEXIBLE 0.5V TO 3.6V 90 REFL REFERENCE 4th OR HIGHER OVDD 85 80 + D11 75 12-BIT • ANALOG INPUT CORRECTION OUTPUT 2nd OR 3rd PIPELINED • INPUT 70 S/H LOGIC DRIVERS ADC CORE • SFDR (dBFS) – D0 65 60 OGND 55 CLOCK/DUTY CYCLE 50 0 100 200 300 400 500 600 CONTROL INPUT FREQUENCY (MHz) 2224 TA01 2224 TA01b ENCODE INPUT 2224fa 1