Datasheet LTC2209 (Analog Devices) - 6
| Hersteller | Analog Devices |
| Beschreibung | 16-Bit, 160Msps ADC |
| Seiten / Seite | 32 / 6 — power requireMents The. denotes the specifications which apply over the … |
| Dateiformat / Größe | PDF / 612 Kb |
| Dokumentensprache | Englisch |
power requireMents The. denotes the specifications which apply over the full operating temperature
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LTC2209
power requireMents The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VDD Analog Supply Voltage (Note 8) l 3.135 3.3 3.465 V PSHDN Shutdown Power SHDN = VDD 0.2 mW
STANDARD LVDS OUTPUT MODE
OVDD Output Supply Voltage (Note 8) l 3 3.3 3.6 V IVDD Analog Supply Current l 467 510 mA IOVDD Output Supply Current l 74 90 mA PDIS Power Dissipation l 1785 1980 mW
LOW POWER LVDS OUTPUT MODE
OVDD Output Supply Voltage (Note 8) l 3 3.3 3.6 V IVDD Analog Supply Current l 467 510 mA IOVDD Output Supply Current l 41.6 50 mA PDIS Power Dissipation l 1678 1848 mW
CMOS OUTPUT MODE
OVDD Output Supply Voltage (Note 8) l 0.5 3.6 V IVDD Analog Supply Current l 464 507 mA PDIS Power Dissipation l 1531 1673 mW
tiMing characteristics The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fS Sampling Frequency (Note 8) l 1 160 MHz tL ENC Low Time Duty Cycle Stabilizer Off (Note 7) l 2.97 3.125 1000 ns Duty Cycle Stabilizer On (Note 7) l 2.1 3.125 1000 ns tH ENC High Time Duty Cycle Stabilizer Off (Note 7) l 2.97 3.125 1000 ns Duty Cycle Stabilizer On (Note 7) l 2.1 3.125 1000 ns tAP Sample-and-Hold Aperture Delay 1 ns
LVDS OUTPUT MODE (STANDARD and LOW POWER)
tD ENC to DATA Delay (Note 7) l 1.3 2.5 3.8 ns tC ENC to CLKOUT Delay (Note 7) l 1.3 2.5 3.8 ns tSKEW DATA to CLKOUT Skew (tC-tD) (Note 7) l –0.6 0 0.6 ns tRISE Output Rise Time 0.5 ns tFALL Output Fall Time 0.5 ns Data Latency Data Latency 7 Cycles
CMOS OUTPUT MODE
tD ENC to DATA Delay (Note 7) l 1.3 2.7 4.0 ns tC ENC to CLKOUT Delay (Note 7) l 1.3 2.7 4.0 ns tSKEW DATA to CLKOUT Skew (tC-tD) (Note 7) l –0.6 0 0.6 ns Data Latency Data Latency Full Rate CMOS 7 Cycles Demuxed 7 Cycles 2209fb 6 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Common Mode Bias Characteristics Digital Inputs and Digital Outputs Power Requirements Timing Characteristics Electrical Characteristics Timing Diagram Typical Performance Characteristics Pin Functions Block Diagram Definitions Applications Information Package Description Revision History Related Parts
power requireMents The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VDD Analog Supply Voltage (Note 8) l 3.135 3.3 3.465 V PSHDN Shutdown Power SHDN = VDD 0.2 mW
STANDARD LVDS OUTPUT MODE
OVDD Output Supply Voltage (Note 8) l 3 3.3 3.6 V IVDD Analog Supply Current l 467 510 mA IOVDD Output Supply Current l 74 90 mA PDIS Power Dissipation l 1785 1980 mW
LOW POWER LVDS OUTPUT MODE
OVDD Output Supply Voltage (Note 8) l 3 3.3 3.6 V IVDD Analog Supply Current l 467 510 mA IOVDD Output Supply Current l 41.6 50 mA PDIS Power Dissipation l 1678 1848 mW
CMOS OUTPUT MODE
OVDD Output Supply Voltage (Note 8) l 0.5 3.6 V IVDD Analog Supply Current l 464 507 mA PDIS Power Dissipation l 1531 1673 mW
tiMing characteristics The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fS Sampling Frequency (Note 8) l 1 160 MHz tL ENC Low Time Duty Cycle Stabilizer Off (Note 7) l 2.97 3.125 1000 ns Duty Cycle Stabilizer On (Note 7) l 2.1 3.125 1000 ns tH ENC High Time Duty Cycle Stabilizer Off (Note 7) l 2.97 3.125 1000 ns Duty Cycle Stabilizer On (Note 7) l 2.1 3.125 1000 ns tAP Sample-and-Hold Aperture Delay 1 ns
LVDS OUTPUT MODE (STANDARD and LOW POWER)
tD ENC to DATA Delay (Note 7) l 1.3 2.5 3.8 ns tC ENC to CLKOUT Delay (Note 7) l 1.3 2.5 3.8 ns tSKEW DATA to CLKOUT Skew (tC-tD) (Note 7) l –0.6 0 0.6 ns tRISE Output Rise Time 0.5 ns tFALL Output Fall Time 0.5 ns Data Latency Data Latency 7 Cycles
CMOS OUTPUT MODE
tD ENC to DATA Delay (Note 7) l 1.3 2.7 4.0 ns tC ENC to CLKOUT Delay (Note 7) l 1.3 2.7 4.0 ns tSKEW DATA to CLKOUT Skew (tC-tD) (Note 7) l –0.6 0 0.6 ns Data Latency Data Latency Full Rate CMOS 7 Cycles Demuxed 7 Cycles 2209fb 6 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Common Mode Bias Characteristics Digital Inputs and Digital Outputs Power Requirements Timing Characteristics Electrical Characteristics Timing Diagram Typical Performance Characteristics Pin Functions Block Diagram Definitions Applications Information Package Description Revision History Related Parts