Datasheet LTC2192, LTC2191, LTC2190 (Analog Devices)
| Hersteller | Analog Devices |
| Beschreibung | 16-Bit, 65Msps Low Power Dual ADCs |
| Seiten / Seite | 28 / 1 — FEATURES. DESCRIPTION. APPLICATIONS. TYPICAL APPLICATION. 2-Tone FFT, fIN … |
| Dateiformat / Größe | PDF / 902 Kb |
| Dokumentensprache | Englisch |
FEATURES. DESCRIPTION. APPLICATIONS. TYPICAL APPLICATION. 2-Tone FFT, fIN = 70MHz and 69MHz
Modelllinie für dieses Datenblatt
- LTC2190CUKG#PBF LTC2190CUKG#PBF LTC2190CUKG#TRPBF LTC2190CUKG#TRPBF LTC2190IUKG#PBF LTC2190IUKG#PBF LTC2190IUKG#TRPBF LTC2190IUKG#TRPBF
Textversion des Dokuments
LTC2192 LTC2191/LTC2190 16-Bit, 65Msps/40Msps/ 25Msps Low Power Dual ADCs
FEATURES DESCRIPTION
n 2-Channel Simultaneous Sampling ADC The LTC®2192/LTC2191/LTC2190 are 2-channel, simul- n Serial LVDS Outputs: 1, 2 or 4 Bits per Channel taneous sampling 16-bit A/D converters designed for n 77dB SNR digitizing high frequency, wide dynamic range signals. They n 90dB SFDR are perfect for demanding communications applications n Low Power: 198mW/146mW/104mW Total with AC performance that includes 77dB SNR and 90dB n 99mW/73mW/52mW per Channel spurious free dynamic range (SFDR). Ultralow jitter of n Single 1.8V Supply 0.07psRMS allows undersampling of IF frequencies with n Selectable Input Ranges: 1VP-P to 2VP-P excellent noise performance. n 550MHz Full-Power Bandwidth S/H DC specs include ±2LSB INL (typ), ±0.5LSB DNL (typ) n Shutdown and Nap Modes and no missing codes over temperature. The transition n Serial SPI Port for Configuration noise is 3.3LSB n RMS. 52-Pin (7mm × 8mm) QFN Package To minimize the number of data lines the digital outputs
APPLICATIONS
are serial LVDS. Each channel outputs one bit, two bits or four bits at a time. The LVDS drivers have optional internal n Communications termination and adjustable output levels to ensure clean n Cellular Base Stations signal integrity. n Software-Defined Radios The ENC+ and ENC– inputs may be driven differentially or n Portable Medical Imaging single ended with a sine wave, PECL, LVDS, TTL or CMOS n Multi-Channel Data Acquisition inputs. An internal clock duty cycle stabilizer allows high n Nondestructive Testing performance at full speed for a wide range of clock duty cycles. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION 2-Tone FFT, fIN = 70MHz and 69MHz
1.8V 1.8V 0 VDD OVDD –10 –20 CH1 OUT1A 16-BIT –30 ANALOG S/H ADC CORE OUT1B INPUT –40 OUT1C –50 OUT1D CH2 SERIALIZED –60 ANALOG 16-BIT OUT2A S/H DATA LVDS INPUT ADC CORE SERIALIZER OUT2B –70 OUTPUTS OUT2C AMPLITUDE (dBFS) –80 ENCODE OUT2D –90 INPUT PLL DATA CLOCK OUT –100 FRAME –110 –120 GND OGND 0 10 20 30 219210 TA01a FREQUENCY (MHz) 219210 G07 219210f 1 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs And Outputs Power Requirements Timing Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Functional Block Diagram Applications Information Typical Applications Package Description Typical Application Related Parts
FEATURES DESCRIPTION
n 2-Channel Simultaneous Sampling ADC The LTC®2192/LTC2191/LTC2190 are 2-channel, simul- n Serial LVDS Outputs: 1, 2 or 4 Bits per Channel taneous sampling 16-bit A/D converters designed for n 77dB SNR digitizing high frequency, wide dynamic range signals. They n 90dB SFDR are perfect for demanding communications applications n Low Power: 198mW/146mW/104mW Total with AC performance that includes 77dB SNR and 90dB n 99mW/73mW/52mW per Channel spurious free dynamic range (SFDR). Ultralow jitter of n Single 1.8V Supply 0.07psRMS allows undersampling of IF frequencies with n Selectable Input Ranges: 1VP-P to 2VP-P excellent noise performance. n 550MHz Full-Power Bandwidth S/H DC specs include ±2LSB INL (typ), ±0.5LSB DNL (typ) n Shutdown and Nap Modes and no missing codes over temperature. The transition n Serial SPI Port for Configuration noise is 3.3LSB n RMS. 52-Pin (7mm × 8mm) QFN Package To minimize the number of data lines the digital outputs
APPLICATIONS
are serial LVDS. Each channel outputs one bit, two bits or four bits at a time. The LVDS drivers have optional internal n Communications termination and adjustable output levels to ensure clean n Cellular Base Stations signal integrity. n Software-Defined Radios The ENC+ and ENC– inputs may be driven differentially or n Portable Medical Imaging single ended with a sine wave, PECL, LVDS, TTL or CMOS n Multi-Channel Data Acquisition inputs. An internal clock duty cycle stabilizer allows high n Nondestructive Testing performance at full speed for a wide range of clock duty cycles. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION 2-Tone FFT, fIN = 70MHz and 69MHz
1.8V 1.8V 0 VDD OVDD –10 –20 CH1 OUT1A 16-BIT –30 ANALOG S/H ADC CORE OUT1B INPUT –40 OUT1C –50 OUT1D CH2 SERIALIZED –60 ANALOG 16-BIT OUT2A S/H DATA LVDS INPUT ADC CORE SERIALIZER OUT2B –70 OUTPUTS OUT2C AMPLITUDE (dBFS) –80 ENCODE OUT2D –90 INPUT PLL DATA CLOCK OUT –100 FRAME –110 –120 GND OGND 0 10 20 30 219210 TA01a FREQUENCY (MHz) 219210 G07 219210f 1 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs And Outputs Power Requirements Timing Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Functional Block Diagram Applications Information Typical Applications Package Description Typical Application Related Parts