Datasheet LTC2107 (Analog Devices) - 7
| Hersteller | Analog Devices |
| Beschreibung | 16-Bit, 210Msps High Performance ADC |
| Seiten / Seite | 32 / 7 — electrical characteristics Note 1:. Note 6:. Note 7:. Note 2:. Note 3:. … |
| Dateiformat / Größe | PDF / 514 Kb |
| Dokumentensprache | Englisch |
electrical characteristics Note 1:. Note 6:. Note 7:. Note 2:. Note 3:. Note 8:. Note 9:. Note 10:. Note 4:. Note 11:. Note 12:. Note 5:
Modelllinie für dieses Datenblatt
Textversion des Dokuments
LTC2107
electrical characteristics Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 6:
Integral nonlinearity is defined as the deviation of a code from a may cause permanent damage to the device. Exposure to any Absolute best fit straight line to the transfer curve. The deviation is measured from Maximum Rating condition for extended periods may affect device the center of the quantization band. reliability and lifetime.
Note 7:
Offset error is the offset voltage measured from –0.5LSB when the
Note 2:
All voltage values are with respect to GND and OGND shorted output code flickers between 0000 0000 0000 0000 and 1111 1111 1111 (unless otherwise noted). 1111 in 2’s complement output mode.
Note 3:
When these pin voltages are taken below GND or above VDD, they
Note 8:
Guaranteed by design, not subject to test. will be clamped by internal diodes. This product can handle input currents
Note 9:
Recommended operating conditions. of greater than 100mA below GND or above VDD without latchup.
Note 10:
Refer to Overflow Bit section for additional information.
Note 4:
When these pin voltages are taken below GND they will be
Note 11:
The test circuit of Figure 11 is used to verify jitter perfomance. clamped by internal diodes. When these pin voltages are taken above VDD they will not be clamped by internal diodes. This product can handle input
Note 12:
CL is the external single-ended load capacitance between each currents of greater than 100mA below GND without latchup. output pin and ground.
Note 5:
VDD = 2.5V, OVDD = 1.8V, fSAMPLE = 210MHz, LVDS outputs, differential ENC+/ENC– = 2VP-P sine wave, input range = 2.4VP-P (PGA = 0) with differential drive, unless otherwise noted.
timing Diagrams CMOS Output Timing Mode All Outputs Are Single-Ended and Have CMOS Levels
tAP ANALOG INPUT N N+1 N+2 N+3 N+4 tH tL ENC– ENC+ tD D0-D15, OF N-7 N-6 N-5 N-4 tC CLKOUT– 2107 TD01 CLKOUT+ 2107fb For more information www.linear.com/LTC2107 7 Document Outline Features Applications Description Block Diagram Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy VCM Output Digital Inputs and OUtputs Power Requirements Timing Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Block Diagram Applications Information Package Description Typical Application Related Parts
electrical characteristics Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 6:
Integral nonlinearity is defined as the deviation of a code from a may cause permanent damage to the device. Exposure to any Absolute best fit straight line to the transfer curve. The deviation is measured from Maximum Rating condition for extended periods may affect device the center of the quantization band. reliability and lifetime.
Note 7:
Offset error is the offset voltage measured from –0.5LSB when the
Note 2:
All voltage values are with respect to GND and OGND shorted output code flickers between 0000 0000 0000 0000 and 1111 1111 1111 (unless otherwise noted). 1111 in 2’s complement output mode.
Note 3:
When these pin voltages are taken below GND or above VDD, they
Note 8:
Guaranteed by design, not subject to test. will be clamped by internal diodes. This product can handle input currents
Note 9:
Recommended operating conditions. of greater than 100mA below GND or above VDD without latchup.
Note 10:
Refer to Overflow Bit section for additional information.
Note 4:
When these pin voltages are taken below GND they will be
Note 11:
The test circuit of Figure 11 is used to verify jitter perfomance. clamped by internal diodes. When these pin voltages are taken above VDD they will not be clamped by internal diodes. This product can handle input
Note 12:
CL is the external single-ended load capacitance between each currents of greater than 100mA below GND without latchup. output pin and ground.
Note 5:
VDD = 2.5V, OVDD = 1.8V, fSAMPLE = 210MHz, LVDS outputs, differential ENC+/ENC– = 2VP-P sine wave, input range = 2.4VP-P (PGA = 0) with differential drive, unless otherwise noted.
timing Diagrams CMOS Output Timing Mode All Outputs Are Single-Ended and Have CMOS Levels
tAP ANALOG INPUT N N+1 N+2 N+3 N+4 tH tL ENC– ENC+ tD D0-D15, OF N-7 N-6 N-5 N-4 tC CLKOUT– 2107 TD01 CLKOUT+ 2107fb For more information www.linear.com/LTC2107 7 Document Outline Features Applications Description Block Diagram Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy VCM Output Digital Inputs and OUtputs Power Requirements Timing Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Block Diagram Applications Information Package Description Typical Application Related Parts