Datasheet LTC1860L, LTC1861L (Analog Devices) - 9
| Hersteller | Analog Devices |
| Beschreibung | µPower, 3V, 12-Bit, 150ksps 1- and 2-Channel ADCs in MSOP |
| Seiten / Seite | 12 / 9 — APPLICATIO S I FOR ATIO. Figure 1. LTC1860L Operating Sequence. Figure 2. … |
| Dateiformat / Größe | PDF / 240 Kb |
| Dokumentensprache | Englisch |
APPLICATIO S I FOR ATIO. Figure 1. LTC1860L Operating Sequence. Figure 2. LTC1860L Transfer Curve
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Textversion des Dokuments
LTC1860L/LTC1861L
U U W U APPLICATIO S I FOR ATIO
CONV tSMPL tCONV SLEEP MODE 1 2 3 4 5 6 7 8 9 10 11 12 SCK DON'T CARE SDO B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0* Hi-Z Hi-Z *AFTER COMPLETING THE DATA TRANSFER, IF FURTHER SCK CLOCKS ARE APPLIED WITH CONV LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY 1860 F01
Figure 1. LTC1860L Operating Sequence
1µF 1 1 1 1 1 1 1 1 1 1 1 1 VCC 1 1 1 1 1 1 1 1 1 1 1 0 • • LTC1860L • 1 8 VREF VCC 2 7 0 0 0 0 0 0 0 0 0 0 0 1 VIN* VIN = 0V TO VCC IN+ SCK SERIAL DATA LINK TO 0 0 0 0 0 0 0 0 0 0 0 0 3 6 0V 1LSB V V V IN– SDO ASIC, PLD, MPU, DSP REF REF REF 4 5 OR SHIFT REGISTERS *VIN = IN+ – IN– – 2LSB – 1LSB GND CONV 1860 F03 1860 F02
Figure 2. LTC1860L Transfer Curve Figure 3. LTC1860L with Rail-to-Rail Input Span LTC1861L OPERATION
given channel selection, the converter will measure the voltage between the two channels indicated by the “+”
Operating Sequence
and “–” signs in the selected row of Table 1. In single-ended The LTC1861L conversion cycle begins with the rising mode, all input channels are measured with respect to edge of CONV. After a period equal to t GND (or AGND). A zero code will occur when the “+” CONV, the conver- sion is finished. If CONV is left high after this time, the input minus the “–” input equals zero. Full scale occurs LTC1861L goes into sleep mode. The LTC1861L’s 2-bit when the “+” input minus the “–” input equals VREF minus data word is clocked into the SDI input on the rising edge 1LSB. See Figure 5. Both the “+” and “–” inputs are of SCK after CONV goes low. Additional inputs on the SDI sampled at the same time so common mode noise is pin are then ignored until the next CONV cycle. The shift rejected. The input span in the SO-8 package is fixed at clock (SCK) synchronizes the data transfer with each bit VREF = VCC. If the “–” input in differential mode is being transmitted on the falling SCK edge and captured on grounded, a rail-to-rail input span will result on the “+” the rising SCK edge in both transmitting and receiving input. systems. The data is transmitted and received simulta-
Reference Input
neously (full duplex). After completing the data transfer, if further SCK clocks are applied with CONV low, SDO will The reference input of the LTC1861L SO-8 package is output zeros indefinitely. See Figure 4. internally tied to VCC. The span of the A/D converter is therefore equal to VCC. The voltage on the reference input
Analog Inputs
of the LTC1861L MSOP package defines the span of the The two bits of the input word (SDI) assign the MUX A/D converter. The LTC1861L MSOP package can operate configuration for the next requested conversion. For a with reference voltages from 1V to VCC. 18601Lf 9
U U W U APPLICATIO S I FOR ATIO
CONV tSMPL tCONV SLEEP MODE 1 2 3 4 5 6 7 8 9 10 11 12 SCK DON'T CARE SDO B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0* Hi-Z Hi-Z *AFTER COMPLETING THE DATA TRANSFER, IF FURTHER SCK CLOCKS ARE APPLIED WITH CONV LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY 1860 F01
Figure 1. LTC1860L Operating Sequence
1µF 1 1 1 1 1 1 1 1 1 1 1 1 VCC 1 1 1 1 1 1 1 1 1 1 1 0 • • LTC1860L • 1 8 VREF VCC 2 7 0 0 0 0 0 0 0 0 0 0 0 1 VIN* VIN = 0V TO VCC IN+ SCK SERIAL DATA LINK TO 0 0 0 0 0 0 0 0 0 0 0 0 3 6 0V 1LSB V V V IN– SDO ASIC, PLD, MPU, DSP REF REF REF 4 5 OR SHIFT REGISTERS *VIN = IN+ – IN– – 2LSB – 1LSB GND CONV 1860 F03 1860 F02
Figure 2. LTC1860L Transfer Curve Figure 3. LTC1860L with Rail-to-Rail Input Span LTC1861L OPERATION
given channel selection, the converter will measure the voltage between the two channels indicated by the “+”
Operating Sequence
and “–” signs in the selected row of Table 1. In single-ended The LTC1861L conversion cycle begins with the rising mode, all input channels are measured with respect to edge of CONV. After a period equal to t GND (or AGND). A zero code will occur when the “+” CONV, the conver- sion is finished. If CONV is left high after this time, the input minus the “–” input equals zero. Full scale occurs LTC1861L goes into sleep mode. The LTC1861L’s 2-bit when the “+” input minus the “–” input equals VREF minus data word is clocked into the SDI input on the rising edge 1LSB. See Figure 5. Both the “+” and “–” inputs are of SCK after CONV goes low. Additional inputs on the SDI sampled at the same time so common mode noise is pin are then ignored until the next CONV cycle. The shift rejected. The input span in the SO-8 package is fixed at clock (SCK) synchronizes the data transfer with each bit VREF = VCC. If the “–” input in differential mode is being transmitted on the falling SCK edge and captured on grounded, a rail-to-rail input span will result on the “+” the rising SCK edge in both transmitting and receiving input. systems. The data is transmitted and received simulta-
Reference Input
neously (full duplex). After completing the data transfer, if further SCK clocks are applied with CONV low, SDO will The reference input of the LTC1861L SO-8 package is output zeros indefinitely. See Figure 4. internally tied to VCC. The span of the A/D converter is therefore equal to VCC. The voltage on the reference input
Analog Inputs
of the LTC1861L MSOP package defines the span of the The two bits of the input word (SDI) assign the MUX A/D converter. The LTC1861L MSOP package can operate configuration for the next requested conversion. For a with reference voltages from 1V to VCC. 18601Lf 9