Datasheet LTC1860, LTC1861 (Analog Devices) - 9

LTC1860/LTC1861
pin FuncTions LTC1860 SDI (Pin 6):
Digital Data Input. The A/D configuration
V
word is shifted into this input.
REF (Pin 1):
Reference Input. The reference input defines the span of the A/D converter and must be kept free of
SDO (Pin 7):
Digital Data Output. The A/D conversion noise with respect to GND. result is shifted out of this output.
IN+, IN– (Pins 2, 3):
Analog Inputs. These inputs must be
SCK (Pin 8):
Shift Clock Input. This clock synchronizes free of noise with respect to GND. the serial data transfer.
GND (Pin 4):
Analog Ground. GND should be tied directly
VCC (Pin 9):
Positive Supply. This supply must be kept to an analog ground plane. free of noise and ripple by bypassing directly to the
CONV (Pin 5):
Convert Input. A logic high on this input analog ground plane. starts the A/D conversion process. If the CONV input is
VREF (Pin 10):
Reference Input. The reference input defines left high after the A/D conversion is finished, the part the span of the A/D converter and must be kept free of powers down. A logic low on this input enables the SDO noise with respect to AGND. pin, allowing the data to be shifted out.
LTC1861 (SO-8 Package) SDO (Pin 6):
Digital Data Output. The A/D conversion result is shifted out of this pin.
CONV (Pin 1):
Convert Input. A logic high on this input starts the A/D conversion process. If the CONV input is
SCK (Pin 7):
Shift Clock Input. This clock synchronizes left high after the A/D conversion is finished, the part the serial data transfer. powers down. A logic low on this input enables the SDO
VCC (Pin 8):
Positive Supply. This supply must be kept pin, allowing the data to be shifted out. free of noise and ripple by bypassing directly to the
CH0, CH1 (Pins 2, 3):
Analog Inputs. These inputs must analog ground plane. be free of noise with respect to GND.
LTC1861 (MSOP Package) GND (Pin 4):
Analog Ground. GND should be tied directly
CONV (Pin 1):
Convert Input. A logic high on this input to an analog ground plane. starts the A/D conversion process. If the CONV input is
SDI (Pin 5):
Digital Data Input. The A/D configuration left high after the A/D conversion is finished, the part word is shifted into this input. powers down. A logic low on this input enables the SDO
SDO (Pin 6):
Digital Data Output. The A/D conversion pin, allowing the data to be shifted out. result is shifted out of this output.
CH0, CH1 (Pins 2, 3):
Analog Inputs. These inputs must
SCK (Pin 7):
Shift Clock Input. This clock synchronizes be free of noise with respect to AGND. the serial data transfer.
AGND (Pin 4):
Analog Ground. AGND should be tied directly
V
to an analog ground plane.
CC (Pin 8):
Positive Supply. This supply must be kept free of noise and ripple by bypassing directly to the analog
DGND (Pin 5):
Digital Ground. DGND should be tied directly ground plane. VREF is tied internally to this pin. to an analog ground plane. 18601fb For more information www.linear.com/LTC1860 9 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Typical Performance Characteristics Pin Functions Block Diagram Applications Information Package Description Typical Application Related Parts